| commit | f233136f2ca25316643b7f409df7af55a762f98a | [log] [tgz] |
|---|---|---|
| author | Orion Hodson <oth@google.com> | Wed Jul 11 15:14:10 2018 +0100 |
| committer | Orion Hodson <oth@google.com> | Thu Sep 06 13:47:10 2018 +0100 |
| tree | a5aee0db607b4dc4d08e695426ebb74abcaabc35 | |
| parent | 9999327c8fbcab1d57f609457d68085ddefb7eb7 [diff] |
ART: Add FlushInstructionPipeline() Use membarrier(MEMBARRIER_CMD_PRIVATE_EXPEDITED), where available, to flush CPU instruction pipelines after JIT code cache updates. This is needed on architectures where TLB updates do not require a TLB shootdown. Bug: 65312375 Bug: 66095511 Bug: 111199492 Test: manual (requires kernel >= 4.16). Change-Id: I96811c611133ba765a546a09432c0c951ad39e10