Add support for int-to-char in the optimizing compiler.
- Add support for the int-to-char Dex instruction in the
optimizing compiler.
- Implement the ARM and Thumb-2 UBFX instructions and add
tests for them.
- Generate x86, x86-64 and ARM (but not ARM64) code for
byte to char, short to char, int to char (and char to
char!) HTypeConversion nodes.
- Add related tests to test/422-type-conversion.
Change-Id: I5cd4c6d86f0f6a966c059715b98db35cc8f9de76
diff --git a/compiler/utils/arm/assembler_arm.h b/compiler/utils/arm/assembler_arm.h
index 911000a..d288b70 100644
--- a/compiler/utils/arm/assembler_arm.h
+++ b/compiler/utils/arm/assembler_arm.h
@@ -421,8 +421,11 @@
virtual void sdiv(Register rd, Register rn, Register rm, Condition cond = AL) = 0;
virtual void udiv(Register rd, Register rn, Register rm, Condition cond = AL) = 0;
+ // Bit field extract instructions.
virtual void sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width,
Condition cond = AL) = 0;
+ virtual void ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width,
+ Condition cond = AL) = 0;
// Load/store instructions.
virtual void ldr(Register rd, const Address& ad, Condition cond = AL) = 0;
diff --git a/compiler/utils/arm/assembler_arm32.cc b/compiler/utils/arm/assembler_arm32.cc
index 29cbf58..39ebf68 100644
--- a/compiler/utils/arm/assembler_arm32.cc
+++ b/compiler/utils/arm/assembler_arm32.cc
@@ -227,6 +227,25 @@
}
+void Arm32Assembler::ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) {
+ CHECK_NE(rd, kNoRegister);
+ CHECK_NE(rn, kNoRegister);
+ CHECK_NE(cond, kNoCondition);
+ CHECK_LE(lsb, 31U);
+ CHECK(1U <= width && width <= 32U) << width;
+ uint32_t widthminus1 = width - 1;
+
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
+ B26 | B25 | B24 | B23 | B22 | B21 |
+ (widthminus1 << 16) |
+ (static_cast<uint32_t>(rd) << 12) |
+ (lsb << 7) |
+ B6 | B4 |
+ static_cast<uint32_t>(rn);
+ Emit(encoding);
+}
+
+
void Arm32Assembler::ldr(Register rd, const Address& ad, Condition cond) {
EmitMemOp(cond, true, false, rd, ad);
}
diff --git a/compiler/utils/arm/assembler_arm32.h b/compiler/utils/arm/assembler_arm32.h
index b582e9e..0b009e1 100644
--- a/compiler/utils/arm/assembler_arm32.h
+++ b/compiler/utils/arm/assembler_arm32.h
@@ -96,7 +96,9 @@
void sdiv(Register rd, Register rn, Register rm, Condition cond = AL) OVERRIDE;
void udiv(Register rd, Register rn, Register rm, Condition cond = AL) OVERRIDE;
+ // Bit field extract instructions.
void sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond = AL) OVERRIDE;
+ void ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond = AL) OVERRIDE;
// Load/store instructions.
void ldr(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
diff --git a/compiler/utils/arm/assembler_arm32_test.cc b/compiler/utils/arm/assembler_arm32_test.cc
index 4f5d4c3..277a9eb 100644
--- a/compiler/utils/arm/assembler_arm32_test.cc
+++ b/compiler/utils/arm/assembler_arm32_test.cc
@@ -116,4 +116,40 @@
DriverStr(expected, "sbfx");
}
+TEST_F(AssemblerArm32Test, Ubfx) {
+ GetAssembler()->ubfx(arm::R0, arm::R1, 0, 1);
+ GetAssembler()->ubfx(arm::R0, arm::R1, 0, 8);
+ GetAssembler()->ubfx(arm::R0, arm::R1, 0, 16);
+ GetAssembler()->ubfx(arm::R0, arm::R1, 0, 32);
+
+ GetAssembler()->ubfx(arm::R0, arm::R1, 8, 1);
+ GetAssembler()->ubfx(arm::R0, arm::R1, 8, 8);
+ GetAssembler()->ubfx(arm::R0, arm::R1, 8, 16);
+ GetAssembler()->ubfx(arm::R0, arm::R1, 8, 24);
+
+ GetAssembler()->ubfx(arm::R0, arm::R1, 16, 1);
+ GetAssembler()->ubfx(arm::R0, arm::R1, 16, 8);
+ GetAssembler()->ubfx(arm::R0, arm::R1, 16, 16);
+
+ GetAssembler()->ubfx(arm::R0, arm::R1, 31, 1);
+
+ const char* expected =
+ "ubfx r0, r1, #0, #1\n"
+ "ubfx r0, r1, #0, #8\n"
+ "ubfx r0, r1, #0, #16\n"
+ "ubfx r0, r1, #0, #32\n"
+
+ "ubfx r0, r1, #8, #1\n"
+ "ubfx r0, r1, #8, #8\n"
+ "ubfx r0, r1, #8, #16\n"
+ "ubfx r0, r1, #8, #24\n"
+
+ "ubfx r0, r1, #16, #1\n"
+ "ubfx r0, r1, #16, #8\n"
+ "ubfx r0, r1, #16, #16\n"
+
+ "ubfx r0, r1, #31, #1\n";
+ DriverStr(expected, "ubfx");
+}
+
} // namespace art
diff --git a/compiler/utils/arm/assembler_thumb2.cc b/compiler/utils/arm/assembler_thumb2.cc
index a309e18..3ab9b2b 100644
--- a/compiler/utils/arm/assembler_thumb2.cc
+++ b/compiler/utils/arm/assembler_thumb2.cc
@@ -285,6 +285,27 @@
}
+void Thumb2Assembler::ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) {
+ CheckCondition(cond);
+ CHECK_LE(lsb, 31U);
+ CHECK(1U <= width && width <= 32U) << width;
+ uint32_t widthminus1 = width - 1;
+ uint32_t imm2 = lsb & (B1 | B0); // Bits 0-1 of `lsb`.
+ uint32_t imm3 = (lsb & (B4 | B3 | B2)) >> 2; // Bits 2-4 of `lsb`.
+
+ uint32_t op = 28U /* 0b11100 */;
+ int32_t encoding = B31 | B30 | B29 | B28 | B25 |
+ op << 20 |
+ static_cast<uint32_t>(rn) << 16 |
+ imm3 << 12 |
+ static_cast<uint32_t>(rd) << 8 |
+ imm2 << 6 |
+ widthminus1;
+
+ Emit32(encoding);
+}
+
+
void Thumb2Assembler::ldr(Register rd, const Address& ad, Condition cond) {
EmitLoadStore(cond, true, false, false, false, rd, ad);
}
diff --git a/compiler/utils/arm/assembler_thumb2.h b/compiler/utils/arm/assembler_thumb2.h
index 1fc842c..cfa251a 100644
--- a/compiler/utils/arm/assembler_thumb2.h
+++ b/compiler/utils/arm/assembler_thumb2.h
@@ -118,7 +118,9 @@
void sdiv(Register rd, Register rn, Register rm, Condition cond = AL) OVERRIDE;
void udiv(Register rd, Register rn, Register rm, Condition cond = AL) OVERRIDE;
+ // Bit field extract instructions.
void sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond = AL) OVERRIDE;
+ void ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond = AL) OVERRIDE;
// Load/store instructions.
void ldr(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
diff --git a/compiler/utils/arm/assembler_thumb2_test.cc b/compiler/utils/arm/assembler_thumb2_test.cc
index 57ba0ca..65d6d45 100644
--- a/compiler/utils/arm/assembler_thumb2_test.cc
+++ b/compiler/utils/arm/assembler_thumb2_test.cc
@@ -120,4 +120,40 @@
DriverStr(expected, "sbfx");
}
+TEST_F(AssemblerThumb2Test, Ubfx) {
+ GetAssembler()->ubfx(arm::R0, arm::R1, 0, 1);
+ GetAssembler()->ubfx(arm::R0, arm::R1, 0, 8);
+ GetAssembler()->ubfx(arm::R0, arm::R1, 0, 16);
+ GetAssembler()->ubfx(arm::R0, arm::R1, 0, 32);
+
+ GetAssembler()->ubfx(arm::R0, arm::R1, 8, 1);
+ GetAssembler()->ubfx(arm::R0, arm::R1, 8, 8);
+ GetAssembler()->ubfx(arm::R0, arm::R1, 8, 16);
+ GetAssembler()->ubfx(arm::R0, arm::R1, 8, 24);
+
+ GetAssembler()->ubfx(arm::R0, arm::R1, 16, 1);
+ GetAssembler()->ubfx(arm::R0, arm::R1, 16, 8);
+ GetAssembler()->ubfx(arm::R0, arm::R1, 16, 16);
+
+ GetAssembler()->ubfx(arm::R0, arm::R1, 31, 1);
+
+ const char* expected =
+ "ubfx r0, r1, #0, #1\n"
+ "ubfx r0, r1, #0, #8\n"
+ "ubfx r0, r1, #0, #16\n"
+ "ubfx r0, r1, #0, #32\n"
+
+ "ubfx r0, r1, #8, #1\n"
+ "ubfx r0, r1, #8, #8\n"
+ "ubfx r0, r1, #8, #16\n"
+ "ubfx r0, r1, #8, #24\n"
+
+ "ubfx r0, r1, #16, #1\n"
+ "ubfx r0, r1, #16, #8\n"
+ "ubfx r0, r1, #16, #16\n"
+
+ "ubfx r0, r1, #31, #1\n";
+ DriverStr(expected, "ubfx");
+}
+
} // namespace art