diff --git a/compiler/optimizing/code_generator_arm64.cc b/compiler/optimizing/code_generator_arm64.cc
index a2896fc..f4e18cf 100644
--- a/compiler/optimizing/code_generator_arm64.cc
+++ b/compiler/optimizing/code_generator_arm64.cc
@@ -3045,6 +3045,13 @@
   return divisor < 0 && magic_number > 0;
 }
 
+// Return true if the result of multiplication of the dividend by a sort of reciprocal
+// of the divisor (magic_number) needs to be corrected. This means additional operations will
+// be generated.
+static inline bool NeedToCorrectMulResult(int64_t magic_number, int64_t divisor) {
+  return NeedToAddDividend(magic_number, divisor) || NeedToSubDividend(magic_number, divisor);
+}
+
 void InstructionCodeGeneratorARM64::GenerateResultDivRemWithAnyConstant(
     bool is_rem,
     int final_right_shift,
@@ -3131,7 +3138,17 @@
   // temp = get_high(dividend * magic)
   __ Mov(temp, magic);
   __ Smull(temp.X(), dividend, temp);
-  __ Lsr(temp.X(), temp.X(), 32);
+
+  if (NeedToCorrectMulResult(magic, imm)) {
+    __ Lsr(temp.X(), temp.X(), 32);
+  } else {
+    // As between 'lsr temp.X(), temp.X(), #32' and 'asr temp, temp, #shift' there are
+    // no other instructions modifying 'temp', they can be combined into one
+    // 'asr temp.X(), temp.X(), #32 + shift'.
+    DCHECK_LT(shift, 32);
+    __ Asr(temp.X(), temp.X(), 32 + shift);
+    shift = 0;
+  }
 
   GenerateResultDivRemWithAnyConstant(/* is_rem= */ instruction->IsRem(),
                                       /* final_right_shift= */ shift,