Improve documentation and assertions of read barrier instrumentation.
For ARM, x86, x86-64 back ends. The case of the ARM64 back
end is already handled in
https://android-review.googlesource.com/#/c/197870/.
Bug: 12687968
Change-Id: I6df1128cc100cbdb89020876e1a54de719508be3
diff --git a/compiler/optimizing/code_generator_x86.h b/compiler/optimizing/code_generator_x86.h
index 43e9543..0aef478 100644
--- a/compiler/optimizing/code_generator_x86.h
+++ b/compiler/optimizing/code_generator_x86.h
@@ -233,23 +233,29 @@
// out <- *(out + offset)
//
// while honoring heap poisoning and/or read barriers (if any).
- // Register `temp` is used when generating a read barrier.
+ //
+ // Location `maybe_temp` is used when generating a read barrier and
+ // shall be a register in that case; it may be an invalid location
+ // otherwise.
void GenerateReferenceLoadOneRegister(HInstruction* instruction,
Location out,
uint32_t offset,
- Location temp);
+ Location maybe_temp);
// Generate a heap reference load using two different registers
// `out` and `obj`:
//
// out <- *(obj + offset)
//
// while honoring heap poisoning and/or read barriers (if any).
- // Register `temp` is used when generating a Baker's read barrier.
+ //
+ // Location `maybe_temp` is used when generating a Baker's (fast
+ // path) read barrier and shall be a register in that case; it may
+ // be an invalid location otherwise.
void GenerateReferenceLoadTwoRegisters(HInstruction* instruction,
Location out,
Location obj,
uint32_t offset,
- Location temp);
+ Location maybe_temp);
// Generate a GC root reference load:
//
// root <- *(obj + offset)