Merge "Do not mention x86 floating point numbers in CFI."
diff --git a/compiler/dwarf/register.h b/compiler/dwarf/register.h
index fa666df..7045237 100644
--- a/compiler/dwarf/register.h
+++ b/compiler/dwarf/register.h
@@ -33,6 +33,7 @@
// There are ways around this in DWARF but they are complex.
// It would be much simpler to always spill whole D registers.
// Arm64 mapping is correct since we already do this there.
+ // libunwind might struggle with the new mapping as well.
static Reg ArmCore(int num) { return Reg(num); }
static Reg ArmFp(int num) { return Reg(64 + num); } // S0–S31.
diff --git a/compiler/elf_writer_debug.cc b/compiler/elf_writer_debug.cc
index cf0adae..28e6999 100644
--- a/compiler/elf_writer_debug.cc
+++ b/compiler/elf_writer_debug.cc
@@ -99,6 +99,8 @@
return;
}
case kX86: {
+ // FIXME: Add fp registers once libunwind adds support for them. Bug: 20491296
+ constexpr bool generate_opcodes_for_x86_fp = false;
DebugFrameOpCodeWriter<> opcodes;
opcodes.DefCFA(Reg::X86Core(4), 4); // R4(ESP).
opcodes.Offset(Reg::X86Core(8), -4); // R8(EIP).
@@ -113,8 +115,10 @@
}
}
// fp registers.
- for (int reg = 0; reg < 8; reg++) {
- opcodes.Undefined(Reg::X86Fp(reg));
+ if (generate_opcodes_for_x86_fp) {
+ for (int reg = 0; reg < 8; reg++) {
+ opcodes.Undefined(Reg::X86Fp(reg));
+ }
}
auto return_reg = Reg::X86Core(8); // R8(EIP).
WriteEhFrameCIE(is64bit, addr_type, return_reg, opcodes, eh_frame);