Rewrite use/def masks to support 128 bits.
Reduce LIR memory usage by holding masks by pointers in the
LIR rather than directly and using pre-defined const masks
for the common cases, allocating very few on the arena.
Change-Id: I0f6d27ef6867acd157184c8c74f9612cebfe6c16
diff --git a/compiler/dex/quick/arm/arm_lir.h b/compiler/dex/quick/arm/arm_lir.h
index e32e7cb..6272555 100644
--- a/compiler/dex/quick/arm/arm_lir.h
+++ b/compiler/dex/quick/arm/arm_lir.h
@@ -109,12 +109,6 @@
kArmRegEnd = 48,
};
-#define ENCODE_ARM_REG_LIST(N) (static_cast<uint64_t>(N))
-#define ENCODE_ARM_REG_SP (1ULL << kArmRegSP)
-#define ENCODE_ARM_REG_LR (1ULL << kArmRegLR)
-#define ENCODE_ARM_REG_PC (1ULL << kArmRegPC)
-#define ENCODE_ARM_REG_FPCS_LIST(N) (static_cast<uint64_t>(N) << kArmFPReg16)
-
enum ArmNativeRegisterPool {
r0 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 0,
r1 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 1,
diff --git a/compiler/dex/quick/arm/call_arm.cc b/compiler/dex/quick/arm/call_arm.cc
index db0731f..5466abd 100644
--- a/compiler/dex/quick/arm/call_arm.cc
+++ b/compiler/dex/quick/arm/call_arm.cc
@@ -87,7 +87,7 @@
tab_rec->anchor = switch_branch;
// Needs to use setflags encoding here
OpRegRegImm(kOpSub, r_idx, r_idx, 1); // For value == 1, this should set flags.
- DCHECK(last_lir_insn_->u.m.def_mask & ENCODE_CCODE);
+ DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode));
OpCondBranch(kCondNe, target);
}
diff --git a/compiler/dex/quick/arm/codegen_arm.h b/compiler/dex/quick/arm/codegen_arm.h
index 9c801a5..c977a23 100644
--- a/compiler/dex/quick/arm/codegen_arm.h
+++ b/compiler/dex/quick/arm/codegen_arm.h
@@ -63,7 +63,7 @@
RegLocation LocCReturnDouble();
RegLocation LocCReturnFloat();
RegLocation LocCReturnWide();
- uint64_t GetRegMaskCommon(RegStorage reg);
+ ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE;
void AdjustSpillMask();
void ClobberCallerSave();
void FreeCallTemps();
@@ -79,12 +79,13 @@
int AssignInsnOffsets();
void AssignOffsets();
static uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir);
- void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);
- void SetupTargetResourceMasks(LIR* lir, uint64_t flags);
+ void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
+ void SetupTargetResourceMasks(LIR* lir, uint64_t flags,
+ ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE;
const char* GetTargetInstFmt(int opcode);
const char* GetTargetInstName(int opcode);
std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
- uint64_t GetPCUseDefEncoding();
+ ResourceMask GetPCUseDefEncoding() const OVERRIDE;
uint64_t GetTargetInstFlags(int opcode);
int GetInsnSize(LIR* lir);
bool IsUnconditionalBranch(LIR* lir);
@@ -217,6 +218,10 @@
bool GetEasyMultiplyOp(int lit, EasyMultiplyOp* op);
bool GetEasyMultiplyTwoOps(int lit, EasyMultiplyOp* ops);
void GenEasyMultiplyTwoOps(RegStorage r_dest, RegStorage r_src, EasyMultiplyOp* ops);
+
+ static constexpr ResourceMask GetRegMaskArm(RegStorage reg);
+ static constexpr ResourceMask EncodeArmRegList(int reg_list);
+ static constexpr ResourceMask EncodeArmRegFpcsList(int reg_list);
};
} // namespace art
diff --git a/compiler/dex/quick/arm/int_arm.cc b/compiler/dex/quick/arm/int_arm.cc
index 4732e52..916c528 100644
--- a/compiler/dex/quick/arm/int_arm.cc
+++ b/compiler/dex/quick/arm/int_arm.cc
@@ -224,13 +224,13 @@
bool cheap_false_val = InexpensiveConstantInt(false_val);
if (cheap_false_val && ccode == kCondEq && (true_val == 0 || true_val == -1)) {
OpRegRegImm(kOpSub, rl_result.reg, rl_src.reg, -true_val);
- DCHECK(last_lir_insn_->u.m.def_mask & ENCODE_CCODE);
+ DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode));
LIR* it = OpIT(true_val == 0 ? kCondNe : kCondUge, "");
LoadConstant(rl_result.reg, false_val);
OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact
} else if (cheap_false_val && ccode == kCondEq && true_val == 1) {
OpRegRegImm(kOpRsub, rl_result.reg, rl_src.reg, 1);
- DCHECK(last_lir_insn_->u.m.def_mask & ENCODE_CCODE);
+ DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode));
LIR* it = OpIT(kCondLs, "");
LoadConstant(rl_result.reg, false_val);
OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact
@@ -882,14 +882,14 @@
}
FreeTemp(r_tmp_high); // Now unneeded
- DCHECK(last_lir_insn_->u.m.def_mask & ENCODE_CCODE);
+ DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode));
it = OpIT(kCondEq, "T");
NewLIR4(kThumb2Strexd /* eq */, r_tmp.GetReg(), rl_new_value.reg.GetLowReg(), rl_new_value.reg.GetHighReg(), r_ptr.GetReg());
} else {
NewLIR3(kThumb2Ldrex, r_tmp.GetReg(), r_ptr.GetReg(), 0);
OpRegReg(kOpSub, r_tmp, rl_expected.reg);
- DCHECK(last_lir_insn_->u.m.def_mask & ENCODE_CCODE);
+ DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode));
it = OpIT(kCondEq, "T");
NewLIR4(kThumb2Strex /* eq */, r_tmp.GetReg(), rl_new_value.reg.GetReg(), r_ptr.GetReg(), 0);
}
@@ -907,7 +907,7 @@
// result := (tmp1 != 0) ? 0 : 1;
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
OpRegRegImm(kOpRsub, rl_result.reg, r_tmp, 1);
- DCHECK(last_lir_insn_->u.m.def_mask & ENCODE_CCODE);
+ DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode));
it = OpIT(kCondUlt, "");
LoadConstant(rl_result.reg, 0); /* cc */
FreeTemp(r_tmp); // Now unneeded.
@@ -971,7 +971,7 @@
LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) {
// Combine sub & test using sub setflags encoding here
OpRegRegImm(kOpSub, reg, reg, 1); // For value == 1, this should set flags.
- DCHECK(last_lir_insn_->u.m.def_mask & ENCODE_CCODE);
+ DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode));
return OpCondBranch(c_code, target);
}
@@ -1004,7 +1004,7 @@
// At this point we must have a memory barrier. Mark it as a scheduling barrier as well.
DCHECK(!barrier->flags.use_def_invalid);
- barrier->u.m.def_mask = ENCODE_ALL;
+ barrier->u.m.def_mask = &kEncodeAll;
return ret;
#else
return false;
diff --git a/compiler/dex/quick/arm/target_arm.cc b/compiler/dex/quick/arm/target_arm.cc
index 3b30cde..e1e2d5b 100644
--- a/compiler/dex/quick/arm/target_arm.cc
+++ b/compiler/dex/quick/arm/target_arm.cc
@@ -135,30 +135,32 @@
/*
* Decode the register id.
*/
-uint64_t ArmMir2Lir::GetRegMaskCommon(RegStorage reg) {
- uint64_t seed;
- int shift;
- int reg_id = reg.GetRegNum();
- /* Each double register is equal to a pair of single-precision FP registers */
- if (reg.IsDouble()) {
- seed = 0x3;
- reg_id = reg_id << 1;
- } else {
- seed = 1;
- }
- /* FP register starts at bit position 16 */
- shift = reg.IsFloat() ? kArmFPReg0 : 0;
- /* Expand the double register id into single offset */
- shift += reg_id;
- return (seed << shift);
+ResourceMask ArmMir2Lir::GetRegMaskCommon(const RegStorage& reg) const {
+ return GetRegMaskArm(reg);
}
-uint64_t ArmMir2Lir::GetPCUseDefEncoding() {
- return ENCODE_ARM_REG_PC;
+constexpr ResourceMask ArmMir2Lir::GetRegMaskArm(RegStorage reg) {
+ return reg.IsDouble()
+ /* Each double register is equal to a pair of single-precision FP registers */
+ ? ResourceMask::TwoBits(reg.GetRegNum() * 2 + kArmFPReg0)
+ : ResourceMask::Bit(reg.IsSingle() ? reg.GetRegNum() + kArmFPReg0 : reg.GetRegNum());
+}
+
+constexpr ResourceMask ArmMir2Lir::EncodeArmRegList(int reg_list) {
+ return ResourceMask::RawMask(static_cast<uint64_t >(reg_list), 0u);
+}
+
+constexpr ResourceMask ArmMir2Lir::EncodeArmRegFpcsList(int reg_list) {
+ return ResourceMask::RawMask(static_cast<uint64_t >(reg_list) << kArmFPReg16, 0u);
+}
+
+ResourceMask ArmMir2Lir::GetPCUseDefEncoding() const {
+ return ResourceMask::Bit(kArmRegPC);
}
// Thumb2 specific setup. TODO: inline?:
-void ArmMir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) {
+void ArmMir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags,
+ ResourceMask* use_mask, ResourceMask* def_mask) {
DCHECK_EQ(cu_->instruction_set, kThumb2);
DCHECK(!lir->flags.use_def_invalid);
@@ -169,70 +171,70 @@
REG_DEF_FPCS_LIST0 | REG_DEF_FPCS_LIST2 | REG_USE_PC | IS_IT | REG_USE_LIST0 |
REG_USE_LIST1 | REG_USE_FPCS_LIST0 | REG_USE_FPCS_LIST2 | REG_DEF_LR)) != 0) {
if (flags & REG_DEF_SP) {
- lir->u.m.def_mask |= ENCODE_ARM_REG_SP;
+ def_mask->SetBit(kArmRegSP);
}
if (flags & REG_USE_SP) {
- lir->u.m.use_mask |= ENCODE_ARM_REG_SP;
+ use_mask->SetBit(kArmRegSP);
}
if (flags & REG_DEF_LIST0) {
- lir->u.m.def_mask |= ENCODE_ARM_REG_LIST(lir->operands[0]);
+ def_mask->SetBits(EncodeArmRegList(lir->operands[0]));
}
if (flags & REG_DEF_LIST1) {
- lir->u.m.def_mask |= ENCODE_ARM_REG_LIST(lir->operands[1]);
+ def_mask->SetBits(EncodeArmRegList(lir->operands[1]));
}
if (flags & REG_DEF_FPCS_LIST0) {
- lir->u.m.def_mask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]);
+ def_mask->SetBits(EncodeArmRegList(lir->operands[0]));
}
if (flags & REG_DEF_FPCS_LIST2) {
for (int i = 0; i < lir->operands[2]; i++) {
- SetupRegMask(&lir->u.m.def_mask, lir->operands[1] + i);
+ SetupRegMask(def_mask, lir->operands[1] + i);
}
}
if (flags & REG_USE_PC) {
- lir->u.m.use_mask |= ENCODE_ARM_REG_PC;
+ use_mask->SetBit(kArmRegPC);
}
/* Conservatively treat the IT block */
if (flags & IS_IT) {
- lir->u.m.def_mask = ENCODE_ALL;
+ *def_mask = kEncodeAll;
}
if (flags & REG_USE_LIST0) {
- lir->u.m.use_mask |= ENCODE_ARM_REG_LIST(lir->operands[0]);
+ use_mask->SetBits(EncodeArmRegList(lir->operands[0]));
}
if (flags & REG_USE_LIST1) {
- lir->u.m.use_mask |= ENCODE_ARM_REG_LIST(lir->operands[1]);
+ use_mask->SetBits(EncodeArmRegList(lir->operands[1]));
}
if (flags & REG_USE_FPCS_LIST0) {
- lir->u.m.use_mask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]);
+ use_mask->SetBits(EncodeArmRegList(lir->operands[0]));
}
if (flags & REG_USE_FPCS_LIST2) {
for (int i = 0; i < lir->operands[2]; i++) {
- SetupRegMask(&lir->u.m.use_mask, lir->operands[1] + i);
+ SetupRegMask(use_mask, lir->operands[1] + i);
}
}
/* Fixup for kThumbPush/lr and kThumbPop/pc */
if (opcode == kThumbPush || opcode == kThumbPop) {
- uint64_t r8Mask = GetRegMaskCommon(rs_r8);
- if ((opcode == kThumbPush) && (lir->u.m.use_mask & r8Mask)) {
- lir->u.m.use_mask &= ~r8Mask;
- lir->u.m.use_mask |= ENCODE_ARM_REG_LR;
- } else if ((opcode == kThumbPop) && (lir->u.m.def_mask & r8Mask)) {
- lir->u.m.def_mask &= ~r8Mask;
- lir->u.m.def_mask |= ENCODE_ARM_REG_PC;
+ constexpr ResourceMask r8Mask = GetRegMaskArm(rs_r8);
+ if ((opcode == kThumbPush) && (use_mask->Intersects(r8Mask))) {
+ use_mask->ClearBits(r8Mask);
+ use_mask->SetBit(kArmRegLR);
+ } else if ((opcode == kThumbPop) && (def_mask->Intersects(r8Mask))) {
+ def_mask->ClearBits(r8Mask);
+ def_mask->SetBit(kArmRegPC);;
}
}
if (flags & REG_DEF_LR) {
- lir->u.m.def_mask |= ENCODE_ARM_REG_LR;
+ def_mask->SetBit(kArmRegLR);
}
}
}
@@ -486,44 +488,44 @@
return buf;
}
-void ArmMir2Lir::DumpResourceMask(LIR* arm_lir, uint64_t mask, const char* prefix) {
+void ArmMir2Lir::DumpResourceMask(LIR* arm_lir, const ResourceMask& mask, const char* prefix) {
char buf[256];
buf[0] = 0;
- if (mask == ENCODE_ALL) {
+ if (mask.Equals(kEncodeAll)) {
strcpy(buf, "all");
} else {
char num[8];
int i;
for (i = 0; i < kArmRegEnd; i++) {
- if (mask & (1ULL << i)) {
+ if (mask.HasBit(i)) {
snprintf(num, arraysize(num), "%d ", i);
strcat(buf, num);
}
}
- if (mask & ENCODE_CCODE) {
+ if (mask.HasBit(ResourceMask::kCCode)) {
strcat(buf, "cc ");
}
- if (mask & ENCODE_FP_STATUS) {
+ if (mask.HasBit(ResourceMask::kFPStatus)) {
strcat(buf, "fpcc ");
}
/* Memory bits */
- if (arm_lir && (mask & ENCODE_DALVIK_REG)) {
+ if (arm_lir && (mask.HasBit(ResourceMask::kDalvikReg))) {
snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s",
DECODE_ALIAS_INFO_REG(arm_lir->flags.alias_info),
DECODE_ALIAS_INFO_WIDE(arm_lir->flags.alias_info) ? "(+1)" : "");
}
- if (mask & ENCODE_LITERAL) {
+ if (mask.HasBit(ResourceMask::kLiteral)) {
strcat(buf, "lit ");
}
- if (mask & ENCODE_HEAP_REF) {
+ if (mask.HasBit(ResourceMask::kHeapRef)) {
strcat(buf, "heap ");
}
- if (mask & ENCODE_MUST_NOT_ALIAS) {
+ if (mask.HasBit(ResourceMask::kMustNotAlias)) {
strcat(buf, "noalias ");
}
}
diff --git a/compiler/dex/quick/arm/utility_arm.cc b/compiler/dex/quick/arm/utility_arm.cc
index 86d32f4..92781b5 100644
--- a/compiler/dex/quick/arm/utility_arm.cc
+++ b/compiler/dex/quick/arm/utility_arm.cc
@@ -87,9 +87,9 @@
if (data_target == NULL) {
data_target = AddWordData(&literal_list_, value);
}
+ ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral);
LIR* load_pc_rel = RawLIR(current_dalvik_offset_, kThumb2Vldrs,
r_dest, rs_r15pc.GetReg(), 0, 0, 0, data_target);
- SetMemRefType(load_pc_rel, true, kLiteral);
AppendLIR(load_pc_rel);
return load_pc_rel;
}
@@ -670,6 +670,7 @@
if (data_target == NULL) {
data_target = AddWideData(&literal_list_, val_lo, val_hi);
}
+ ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral);
if (r_dest.IsFloat()) {
res = RawLIR(current_dalvik_offset_, kThumb2Vldrd,
r_dest.GetReg(), rs_r15pc.GetReg(), 0, 0, 0, data_target);
@@ -678,7 +679,6 @@
res = RawLIR(current_dalvik_offset_, kThumb2LdrdPcRel8,
r_dest.GetLowReg(), r_dest.GetHighReg(), rs_r15pc.GetReg(), 0, 0, data_target);
}
- SetMemRefType(res, true, kLiteral);
AppendLIR(res);
}
return res;
@@ -946,7 +946,8 @@
}
// TODO: in future may need to differentiate Dalvik accesses w/ spills
- if (r_base == rs_rARM_SP) {
+ if (mem_ref_type_ == ResourceMask::kDalvikReg) {
+ DCHECK(r_base == rs_rARM_SP);
AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, r_dest.Is64Bit());
}
return load;
@@ -1085,7 +1086,8 @@
}
// TODO: In future, may need to differentiate Dalvik & spill accesses
- if (r_base == rs_rARM_SP) {
+ if (mem_ref_type_ == ResourceMask::kDalvikReg) {
+ DCHECK(r_base == rs_rARM_SP);
AnnotateDalvikRegAccess(store, displacement >> 2, false /* is_load */, r_src.Is64Bit());
}
return store;