ART: Change temporaries to positive names
Changes compiler temporaries to have positive names. The numbering now
puts them above the code VRs (locals + ins, in that order). The patch also
introduces APIs to query the number of temporaries, locals and ins.
The compiler temp infrastructure suffered from several issues
which are also addressed by this patch:
-There is no longer a queue of compiler temps. This would be polluted
with Method* when post opts were called multiple times.
-Sanity checks have been added to allow requesting of temps from BE
and to prevent temps after frame is committed.
-None of the structures holding temps can overflow because they are
allocated to allow holding maximum temps. Thus temps can be requested
by BE with no problem.
-Since the queue of compiler temps is no longer maintained, it is no
longer possible to refer to a temp that has invalid ssa (because it
was requested before ssa was run).
-The BE can now request temps after all ME allocations and it is guaranteed
to actually receive them.
-ME temps are now treated like normal VRs in all cases with no special
handling. Only the BE temps are handled specially because there are no
references to them from MIRs.
-Deprecated and removed several fields in CompilationUnit that saved
register information and updated callsites to call the new interface from
MIRGraph.
Change-Id: Ia8b1fec9384a1a83017800a59e5b0498dfb2698c
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
diff --git a/compiler/dex/quick/arm/call_arm.cc b/compiler/dex/quick/arm/call_arm.cc
index 4ba3c4b..fc98d31 100644
--- a/compiler/dex/quick/arm/call_arm.cc
+++ b/compiler/dex/quick/arm/call_arm.cc
@@ -44,7 +44,7 @@
* cbnz r_idx, lp
*/
void ArmMir2Lir::GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) {
- const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
+ const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
if (cu_->verbose) {
DumpSparseSwitchTable(table);
}
@@ -92,7 +92,7 @@
void ArmMir2Lir::GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) {
- const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
+ const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
if (cu_->verbose) {
DumpPackedSwitchTable(table);
}
@@ -147,8 +147,8 @@
*
* Total size is 4+(width * size + 1)/2 16-bit code units.
*/
-void ArmMir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) {
- const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
+void ArmMir2Lir::GenFillArrayData(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
+ const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
// Add the table to the list - we'll process it later
FillArrayData *tab_rec =
static_cast<FillArrayData*>(arena_->Alloc(sizeof(FillArrayData), kArenaAllocData));
diff --git a/compiler/dex/quick/arm/codegen_arm.h b/compiler/dex/quick/arm/codegen_arm.h
index 66a98ba..84881e0 100644
--- a/compiler/dex/quick/arm/codegen_arm.h
+++ b/compiler/dex/quick/arm/codegen_arm.h
@@ -117,7 +117,7 @@
void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
void GenExitSequence();
void GenSpecialExitSequence();
- void GenFillArrayData(DexOffset table_offset, RegLocation rl_src);
+ void GenFillArrayData(MIR* mir, DexOffset table_offset, RegLocation rl_src);
void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
void GenSelect(BasicBlock* bb, MIR* mir);
diff --git a/compiler/dex/quick/arm64/call_arm64.cc b/compiler/dex/quick/arm64/call_arm64.cc
index eddc3a3..b9c0990 100644
--- a/compiler/dex/quick/arm64/call_arm64.cc
+++ b/compiler/dex/quick/arm64/call_arm64.cc
@@ -44,7 +44,7 @@
* quit:
*/
void Arm64Mir2Lir::GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) {
- const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
+ const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
if (cu_->verbose) {
DumpSparseSwitchTable(table);
}
@@ -96,7 +96,7 @@
void Arm64Mir2Lir::GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) {
- const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
+ const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
if (cu_->verbose) {
DumpPackedSwitchTable(table);
}
@@ -156,8 +156,8 @@
*
* Total size is 4+(width * size + 1)/2 16-bit code units.
*/
-void Arm64Mir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) {
- const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
+void Arm64Mir2Lir::GenFillArrayData(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
+ const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
// Add the table to the list - we'll process it later
FillArrayData *tab_rec =
static_cast<FillArrayData*>(arena_->Alloc(sizeof(FillArrayData), kArenaAllocData));
diff --git a/compiler/dex/quick/arm64/codegen_arm64.h b/compiler/dex/quick/arm64/codegen_arm64.h
index cc3f90a..1c40292 100644
--- a/compiler/dex/quick/arm64/codegen_arm64.h
+++ b/compiler/dex/quick/arm64/codegen_arm64.h
@@ -183,7 +183,7 @@
void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE;
void GenExitSequence() OVERRIDE;
void GenSpecialExitSequence() OVERRIDE;
- void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) OVERRIDE;
+ void GenFillArrayData(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE;
void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) OVERRIDE;
void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) OVERRIDE;
void GenSelect(BasicBlock* bb, MIR* mir) OVERRIDE;
diff --git a/compiler/dex/quick/arm64/target_arm64.cc b/compiler/dex/quick/arm64/target_arm64.cc
index bb21c7f..0b58fb1 100644
--- a/compiler/dex/quick/arm64/target_arm64.cc
+++ b/compiler/dex/quick/arm64/target_arm64.cc
@@ -893,11 +893,11 @@
RegStorage Arm64Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) {
if (!in_to_reg_storage_mapping_.IsInitialized()) {
- int start_vreg = cu_->num_dalvik_registers - cu_->num_ins;
+ int start_vreg = mir_graph_->GetFirstInVR();
RegLocation* arg_locs = &mir_graph_->reg_location_[start_vreg];
InToRegStorageArm64Mapper mapper;
- in_to_reg_storage_mapping_.Initialize(arg_locs, cu_->num_ins, &mapper);
+ in_to_reg_storage_mapping_.Initialize(arg_locs, mir_graph_->GetNumOfInVRs(), &mapper);
}
return in_to_reg_storage_mapping_.Get(arg_num);
}
@@ -931,14 +931,14 @@
StoreRefDisp(TargetPtrReg(kSp), 0, rl_src.reg, kNotVolatile);
}
- if (cu_->num_ins == 0) {
+ if (mir_graph_->GetNumOfInVRs() == 0) {
return;
}
// Handle dalvik registers.
ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
- int start_vreg = cu_->num_dalvik_registers - cu_->num_ins;
- for (int i = 0; i < cu_->num_ins; i++) {
+ int start_vreg = mir_graph_->GetFirstInVR();
+ for (uint32_t i = 0; i < mir_graph_->GetNumOfInVRs(); i++) {
RegLocation* t_loc = &ArgLocs[i];
OpSize op_size;
RegStorage reg = GetArgPhysicalReg(t_loc, &num_gpr_used, &num_fpr_used, &op_size);
@@ -1081,9 +1081,6 @@
}
}
- // Logic below assumes that Method pointer is at offset zero from SP.
- DCHECK_EQ(VRegOffset(static_cast<int>(kVRegMethodPtrBaseReg)), 0);
-
// The rest can be copied together
int start_offset = SRegOffset(info->args[last_mapped_in + 1].s_reg_low);
int outs_offset = StackVisitor::GetOutVROffset(last_mapped_in + 1,
diff --git a/compiler/dex/quick/codegen_util.cc b/compiler/dex/quick/codegen_util.cc
index ebebe70..08e1c1a 100644
--- a/compiler/dex/quick/codegen_util.cc
+++ b/compiler/dex/quick/codegen_util.cc
@@ -268,8 +268,8 @@
}
void Mir2Lir::DumpPromotionMap() {
- int num_regs = cu_->num_dalvik_registers + mir_graph_->GetNumUsedCompilerTemps();
- for (int i = 0; i < num_regs; i++) {
+ uint32_t num_regs = mir_graph_->GetNumOfCodeAndTempVRs();
+ for (uint32_t i = 0; i < num_regs; i++) {
PromotionMap v_reg_map = promotion_map_[i];
std::string buf;
if (v_reg_map.fp_location == kLocPhysReg) {
@@ -277,12 +277,13 @@
}
std::string buf3;
- if (i < cu_->num_dalvik_registers) {
+ if (i < mir_graph_->GetNumOfCodeVRs()) {
StringAppendF(&buf3, "%02d", i);
- } else if (i == mir_graph_->GetMethodSReg()) {
+ } else if (i == mir_graph_->GetNumOfCodeVRs()) {
buf3 = "Method*";
} else {
- StringAppendF(&buf3, "ct%d", i - cu_->num_dalvik_registers);
+ uint32_t diff = i - mir_graph_->GetNumOfCodeVRs();
+ StringAppendF(&buf3, "ct%d", diff);
}
LOG(INFO) << StringPrintf("V[%s] -> %s%d%s", buf3.c_str(),
@@ -313,9 +314,9 @@
LIR* lir_insn;
int insns_size = cu_->code_item->insns_size_in_code_units_;
- LOG(INFO) << "Regs (excluding ins) : " << cu_->num_regs;
- LOG(INFO) << "Ins : " << cu_->num_ins;
- LOG(INFO) << "Outs : " << cu_->num_outs;
+ LOG(INFO) << "Regs (excluding ins) : " << mir_graph_->GetNumOfLocalCodeVRs();
+ LOG(INFO) << "Ins : " << mir_graph_->GetNumOfInVRs();
+ LOG(INFO) << "Outs : " << mir_graph_->GetNumOfOutVRs();
LOG(INFO) << "CoreSpills : " << num_core_spills_;
LOG(INFO) << "FPSpills : " << num_fp_spills_;
LOG(INFO) << "CompilerTemps : " << mir_graph_->GetNumUsedCompilerTemps();
@@ -1117,7 +1118,8 @@
// By default assume that the Mir2Lir will need one slot for each temporary.
// If the backend can better determine temps that have non-overlapping ranges and
// temps that do not need spilled, it can actually provide a small region.
- return (mir_graph_->GetNumUsedCompilerTemps() * sizeof(uint32_t));
+ mir_graph_->CommitCompilerTemps();
+ return mir_graph_->GetNumBytesForSpecialTemps() + mir_graph_->GetMaximumBytesForNonSpecialTemps();
}
int Mir2Lir::ComputeFrameSize() {
@@ -1125,7 +1127,8 @@
uint32_t size = num_core_spills_ * GetBytesPerGprSpillLocation(cu_->instruction_set)
+ num_fp_spills_ * GetBytesPerFprSpillLocation(cu_->instruction_set)
+ sizeof(uint32_t) // Filler.
- + (cu_->num_regs + cu_->num_outs) * sizeof(uint32_t)
+ + mir_graph_->GetNumOfLocalCodeVRs() * sizeof(uint32_t)
+ + mir_graph_->GetNumOfOutVRs() * sizeof(uint32_t)
+ GetNumBytesForCompilerTempSpillRegion();
/* Align and set */
return RoundUp(size, kStackAlignment);
diff --git a/compiler/dex/quick/gen_common.cc b/compiler/dex/quick/gen_common.cc
index b2af298..fbe710b 100644
--- a/compiler/dex/quick/gen_common.cc
+++ b/compiler/dex/quick/gen_common.cc
@@ -2105,7 +2105,7 @@
}
void Mir2Lir::GenSmallPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
- const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
+ const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
const uint16_t entries = table[1];
// Chained cmp-and-branch.
const int32_t* as_int32 = reinterpret_cast<const int32_t*>(&table[2]);
@@ -2148,7 +2148,7 @@
}
void Mir2Lir::GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
- const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
+ const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
if (cu_->verbose) {
DumpSparseSwitchTable(table);
}
@@ -2163,7 +2163,7 @@
}
void Mir2Lir::GenSmallSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
- const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
+ const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
const uint16_t entries = table[1];
// Chained cmp-and-branch.
const int32_t* keys = reinterpret_cast<const int32_t*>(&table[2]);
@@ -2178,7 +2178,7 @@
}
void Mir2Lir::GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
- const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
+ const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
if (cu_->verbose) {
DumpSparseSwitchTable(table);
}
diff --git a/compiler/dex/quick/gen_invoke.cc b/compiler/dex/quick/gen_invoke.cc
index 3fdbe20..e1d3241 100755
--- a/compiler/dex/quick/gen_invoke.cc
+++ b/compiler/dex/quick/gen_invoke.cc
@@ -381,11 +381,11 @@
StoreRefDisp(TargetPtrReg(kSp), 0, rl_src.reg, kNotVolatile);
}
- if (cu_->num_ins == 0) {
+ if (mir_graph_->GetNumOfInVRs() == 0) {
return;
}
- int start_vreg = cu_->num_dalvik_registers - cu_->num_ins;
+ int start_vreg = mir_graph_->GetFirstInVR();
/*
* Copy incoming arguments to their proper home locations.
* NOTE: an older version of dx had an issue in which
@@ -399,7 +399,7 @@
* half to memory as well.
*/
ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
- for (int i = 0; i < cu_->num_ins; i++) {
+ for (uint32_t i = 0; i < mir_graph_->GetNumOfInVRs(); i++) {
PromotionMap* v_map = &promotion_map_[start_vreg + i];
RegStorage reg = GetArgMappingToPhysicalReg(i);
@@ -933,9 +933,6 @@
}
}
- // Logic below assumes that Method pointer is at offset zero from SP.
- DCHECK_EQ(VRegOffset(static_cast<int>(kVRegMethodPtrBaseReg)), 0);
-
// The first 3 arguments are passed via registers.
// TODO: For 64-bit, instead of hardcoding 4 for Method* size, we should either
// get size of uintptr_t or size of object reference according to model being used.
diff --git a/compiler/dex/quick/mips/call_mips.cc b/compiler/dex/quick/mips/call_mips.cc
index e8cb356..f3edd7e 100644
--- a/compiler/dex/quick/mips/call_mips.cc
+++ b/compiler/dex/quick/mips/call_mips.cc
@@ -62,7 +62,7 @@
*
*/
void MipsMir2Lir::GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
- const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
+ const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
if (cu_->verbose) {
DumpSparseSwitchTable(table);
}
@@ -139,7 +139,7 @@
* done:
*/
void MipsMir2Lir::GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
- const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
+ const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
if (cu_->verbose) {
DumpPackedSwitchTable(table);
}
@@ -220,8 +220,8 @@
*
* Total size is 4+(width * size + 1)/2 16-bit code units.
*/
-void MipsMir2Lir::GenFillArrayData(DexOffset table_offset, RegLocation rl_src) {
- const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
+void MipsMir2Lir::GenFillArrayData(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
+ const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
// Add the table to the list - we'll process it later
FillArrayData* tab_rec =
reinterpret_cast<FillArrayData*>(arena_->Alloc(sizeof(FillArrayData),
diff --git a/compiler/dex/quick/mips/codegen_mips.h b/compiler/dex/quick/mips/codegen_mips.h
index 9f1af69..be94019 100644
--- a/compiler/dex/quick/mips/codegen_mips.h
+++ b/compiler/dex/quick/mips/codegen_mips.h
@@ -116,7 +116,7 @@
void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
void GenExitSequence();
void GenSpecialExitSequence();
- void GenFillArrayData(uint32_t table_offset, RegLocation rl_src);
+ void GenFillArrayData(MIR* mir, DexOffset table_offset, RegLocation rl_src);
void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
void GenSelect(BasicBlock* bb, MIR* mir);
diff --git a/compiler/dex/quick/mir_to_lir.cc b/compiler/dex/quick/mir_to_lir.cc
index 3ec37f2..96f00e7 100644
--- a/compiler/dex/quick/mir_to_lir.cc
+++ b/compiler/dex/quick/mir_to_lir.cc
@@ -599,7 +599,7 @@
break;
case Instruction::FILL_ARRAY_DATA:
- GenFillArrayData(vB, rl_src[0]);
+ GenFillArrayData(mir, vB, rl_src[0]);
break;
case Instruction::FILLED_NEW_ARRAY:
@@ -1200,9 +1200,8 @@
if (bb->block_type == kEntryBlock) {
ResetRegPool();
- int start_vreg = cu_->num_dalvik_registers - cu_->num_ins;
- GenEntrySequence(&mir_graph_->reg_location_[start_vreg],
- mir_graph_->reg_location_[mir_graph_->GetMethodSReg()]);
+ int start_vreg = mir_graph_->GetFirstInVR();
+ GenEntrySequence(&mir_graph_->reg_location_[start_vreg], mir_graph_->GetMethodLoc());
} else if (bb->block_type == kExitBlock) {
ResetRegPool();
GenExitSequence();
diff --git a/compiler/dex/quick/mir_to_lir.h b/compiler/dex/quick/mir_to_lir.h
index d101a13..d6fc2e9 100644
--- a/compiler/dex/quick/mir_to_lir.h
+++ b/compiler/dex/quick/mir_to_lir.h
@@ -1313,7 +1313,7 @@
virtual void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) = 0;
virtual void GenExitSequence() = 0;
- virtual void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) = 0;
+ virtual void GenFillArrayData(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0;
virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) = 0;
virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0;
diff --git a/compiler/dex/quick/quick_compiler.cc b/compiler/dex/quick/quick_compiler.cc
index 9691864..49c16cb 100644
--- a/compiler/dex/quick/quick_compiler.cc
+++ b/compiler/dex/quick/quick_compiler.cc
@@ -495,8 +495,8 @@
bool QuickCompiler::CanCompileMethod(uint32_t method_idx, const DexFile& dex_file,
CompilationUnit* cu) const {
// This is a limitation in mir_graph. See MirGraph::SetNumSSARegs.
- if (cu->num_dalvik_registers > kMaxAllowedDalvikRegisters) {
- VLOG(compiler) << "Too many dalvik registers : " << cu->num_dalvik_registers;
+ if (cu->mir_graph->GetNumOfCodeAndTempVRs() > kMaxAllowedDalvikRegisters) {
+ VLOG(compiler) << "Too many dalvik registers : " << cu->mir_graph->GetNumOfCodeAndTempVRs();
return false;
}
diff --git a/compiler/dex/quick/ralloc_util.cc b/compiler/dex/quick/ralloc_util.cc
index 4021c95..0a737a9 100644
--- a/compiler/dex/quick/ralloc_util.cc
+++ b/compiler/dex/quick/ralloc_util.cc
@@ -252,20 +252,7 @@
DCHECK_LT(s_reg, mir_graph_->GetNumSSARegs());
DCHECK_GE(s_reg, 0);
int v_reg = mir_graph_->SRegToVReg(s_reg);
- if (v_reg >= 0) {
- DCHECK_LT(v_reg, cu_->num_dalvik_registers);
- return v_reg;
- } else {
- /*
- * It must be the case that the v_reg for temporary is less than or equal to the
- * base reg for temps. For that reason, "position" must be zero or positive.
- */
- unsigned int position = std::abs(v_reg) - std::abs(static_cast<int>(kVRegTempBaseReg));
-
- // The temporaries are placed after dalvik registers in the promotion map
- DCHECK_LT(position, mir_graph_->GetNumUsedCompilerTemps());
- return cu_->num_dalvik_registers + position;
- }
+ return v_reg;
}
// TODO: refactor following Alloc/Record routines - much commonality.
@@ -1211,8 +1198,7 @@
* optimization is disabled.
*/
void Mir2Lir::DoPromotion() {
- int dalvik_regs = cu_->num_dalvik_registers;
- int num_regs = dalvik_regs + mir_graph_->GetNumUsedCompilerTemps();
+ int num_regs = mir_graph_->GetNumOfCodeAndTempVRs();
const int promotion_threshold = 1;
// Allocate the promotion map - one entry for each Dalvik vReg or compiler temp
promotion_map_ = static_cast<PromotionMap*>
@@ -1241,17 +1227,10 @@
static_cast<RefCounts *>(arena_->Alloc(sizeof(RefCounts) * fp_reg_count_size,
kArenaAllocRegAlloc));
// Set ssa names for original Dalvik registers
- for (int i = 0; i < dalvik_regs; i++) {
+ for (int i = 0; i < num_regs; i++) {
core_regs[i].s_reg = fp_regs[i].s_reg = i;
}
- // Set ssa names for compiler temporaries
- for (unsigned int ct_idx = 0; ct_idx < mir_graph_->GetNumUsedCompilerTemps(); ct_idx++) {
- CompilerTemp* ct = mir_graph_->GetCompilerTemp(ct_idx);
- core_regs[dalvik_regs + ct_idx].s_reg = ct->s_reg_low;
- fp_regs[dalvik_regs + ct_idx].s_reg = ct->s_reg_low;
- }
-
// Duplicate in upper half to represent possible wide starting sregs.
for (size_t i = num_regs; i < fp_reg_count_size; i++) {
fp_regs[i].s_reg = fp_regs[i - num_regs].s_reg | STARTING_WIDE_SREG;
diff --git a/compiler/dex/quick/x86/call_x86.cc b/compiler/dex/quick/x86/call_x86.cc
index 996689a..482c430 100644
--- a/compiler/dex/quick/x86/call_x86.cc
+++ b/compiler/dex/quick/x86/call_x86.cc
@@ -28,7 +28,7 @@
* pairs.
*/
void X86Mir2Lir::GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
- const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
+ const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
if (cu_->verbose) {
DumpSparseSwitchTable(table);
}
@@ -61,7 +61,7 @@
* done:
*/
void X86Mir2Lir::GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
- const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
+ const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
if (cu_->verbose) {
DumpPackedSwitchTable(table);
}
@@ -134,8 +134,8 @@
*
* Total size is 4+(width * size + 1)/2 16-bit code units.
*/
-void X86Mir2Lir::GenFillArrayData(DexOffset table_offset, RegLocation rl_src) {
- const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
+void X86Mir2Lir::GenFillArrayData(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
+ const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
// Add the table to the list - we'll process it later
FillArrayData* tab_rec =
static_cast<FillArrayData*>(arena_->Alloc(sizeof(FillArrayData), kArenaAllocData));
diff --git a/compiler/dex/quick/x86/codegen_x86.h b/compiler/dex/quick/x86/codegen_x86.h
index aeeaea2..7ad917d 100644
--- a/compiler/dex/quick/x86/codegen_x86.h
+++ b/compiler/dex/quick/x86/codegen_x86.h
@@ -235,7 +235,7 @@
void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE;
void GenExitSequence() OVERRIDE;
void GenSpecialExitSequence() OVERRIDE;
- void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) OVERRIDE;
+ void GenFillArrayData(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE;
void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) OVERRIDE;
void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) OVERRIDE;
void GenSelect(BasicBlock* bb, MIR* mir) OVERRIDE;
diff --git a/compiler/dex/quick/x86/target_x86.cc b/compiler/dex/quick/x86/target_x86.cc
index c43a1ff..68c1633 100755
--- a/compiler/dex/quick/x86/target_x86.cc
+++ b/compiler/dex/quick/x86/target_x86.cc
@@ -2234,11 +2234,11 @@
}
if (!in_to_reg_storage_mapping_.IsInitialized()) {
- int start_vreg = cu_->num_dalvik_registers - cu_->num_ins;
+ int start_vreg = cu_->mir_graph->GetFirstInVR();
RegLocation* arg_locs = &mir_graph_->reg_location_[start_vreg];
InToRegStorageX86_64Mapper mapper(this);
- in_to_reg_storage_mapping_.Initialize(arg_locs, cu_->num_ins, &mapper);
+ in_to_reg_storage_mapping_.Initialize(arg_locs, mir_graph_->GetNumOfInVRs(), &mapper);
}
return in_to_reg_storage_mapping_.Get(arg_num);
}
@@ -2287,11 +2287,11 @@
StoreRefDisp(rs_rX86_SP, 0, As32BitReg(TargetReg(kArg0, kRef)), kNotVolatile);
}
- if (cu_->num_ins == 0) {
+ if (mir_graph_->GetNumOfInVRs() == 0) {
return;
}
- int start_vreg = cu_->num_dalvik_registers - cu_->num_ins;
+ int start_vreg = cu_->mir_graph->GetFirstInVR();
/*
* Copy incoming arguments to their proper home locations.
* NOTE: an older version of dx had an issue in which
@@ -2305,7 +2305,7 @@
* half to memory as well.
*/
ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
- for (int i = 0; i < cu_->num_ins; i++) {
+ for (uint32_t i = 0; i < mir_graph_->GetNumOfInVRs(); i++) {
// get reg corresponding to input
RegStorage reg = GetArgMappingToPhysicalReg(i);
@@ -2437,9 +2437,6 @@
}
}
- // Logic below assumes that Method pointer is at offset zero from SP.
- DCHECK_EQ(VRegOffset(static_cast<int>(kVRegMethodPtrBaseReg)), 0);
-
// The rest can be copied together
int start_offset = SRegOffset(info->args[last_mapped_in + size_of_the_last_mapped].s_reg_low);
int outs_offset = StackVisitor::GetOutVROffset(last_mapped_in + size_of_the_last_mapped,
diff --git a/compiler/dex/quick/x86/utility_x86.cc b/compiler/dex/quick/x86/utility_x86.cc
index 037dfed..022fd80 100644
--- a/compiler/dex/quick/x86/utility_x86.cc
+++ b/compiler/dex/quick/x86/utility_x86.cc
@@ -957,7 +957,8 @@
// Did we need a pointer to the method code?
if (store_method_addr_) {
- base_of_code_ = mir_graph_->GetNewCompilerTemp(kCompilerTempVR, cu_->target64 == true);
+ base_of_code_ = mir_graph_->GetNewCompilerTemp(kCompilerTempBackend, cu_->target64 == true);
+ DCHECK(base_of_code_ != nullptr);
} else {
base_of_code_ = nullptr;
}
diff --git a/compiler/dex/quick/x86/x86_lir.h b/compiler/dex/quick/x86/x86_lir.h
index 15fe7e2..e3ef8c1 100644
--- a/compiler/dex/quick/x86/x86_lir.h
+++ b/compiler/dex/quick/x86/x86_lir.h
@@ -75,33 +75,36 @@
* ST1 .. ST7: caller save
*
* Stack frame diagram (stack grows down, higher addresses at top):
+ * For a more detailed view of each region see stack.h.
*
- * +------------------------+
- * | IN[ins-1] | {Note: resides in caller's frame}
- * | . |
- * | IN[0] |
- * | caller's Method* |
- * +========================+ {Note: start of callee's frame}
- * | return address | {pushed by call}
- * | spill region | {variable sized}
- * +------------------------+
- * | ...filler word... | {Note: used as 2nd word of V[locals-1] if long]
- * +------------------------+
- * | V[locals-1] |
- * | V[locals-2] |
- * | . |
- * | . |
- * | V[1] |
- * | V[0] |
- * +------------------------+
- * | 0 to 3 words padding |
- * +------------------------+
- * | OUT[outs-1] |
- * | OUT[outs-2] |
- * | . |
- * | OUT[0] |
- * | cur_method* | <<== sp w/ 16-byte alignment
- * +========================+
+ * +---------------------------+
+ * | IN[ins-1] | {Note: resides in caller's frame}
+ * | . |
+ * | IN[0] |
+ * | caller's Method* |
+ * +===========================+ {Note: start of callee's frame}
+ * | return address | {pushed by call}
+ * | spill region | {variable sized}
+ * +---------------------------+
+ * | ...filler 4-bytes... | {Note: used as 2nd word of V[locals-1] if long]
+ * +---------------------------+
+ * | V[locals-1] |
+ * | V[locals-2] |
+ * | . |
+ * | . |
+ * | V[1] |
+ * | V[0] |
+ * +---------------------------+
+ * | 0 to 12-bytes padding |
+ * +---------------------------+
+ * | compiler temp region |
+ * +---------------------------+
+ * | OUT[outs-1] |
+ * | OUT[outs-2] |
+ * | . |
+ * | OUT[0] |
+ * | StackReference<ArtMethod> | <<== sp w/ 16-byte alignment
+ * +===========================+
*/
enum X86ResourceEncodingPos {