ART: Implement predicated SIMD vectorization.
This CL brings support for predicated execution for
auto-vectorizer and implements arm64 SVE vector backend.
This version passes all the VIXL simulator-runnable tests in
SVE mode with checker off (as all VecOp CHECKs need to be
adjusted for an extra input) and all tests in NEON mode.
Test: art SIMD tests on VIXL simulator.
Test: art tests on FVP (steps in test/README.arm_fvp.md)
Change-Id: Ib78bde31a15e6713d875d6668ad4458f5519605f
diff --git a/compiler/optimizing/loop_optimization.h b/compiler/optimizing/loop_optimization.h
index 0c35f29..0d76804 100644
--- a/compiler/optimizing/loop_optimization.h
+++ b/compiler/optimizing/loop_optimization.h
@@ -76,13 +76,14 @@
kNoShr = 1 << 3, // no arithmetic shift right
kNoHiBits = 1 << 4, // "wider" operations cannot bring in higher order bits
kNoSignedHAdd = 1 << 5, // no signed halving add
- kNoUnroundedHAdd = 1 << 6, // no unrounded halving add
- kNoAbs = 1 << 7, // no absolute value
- kNoStringCharAt = 1 << 8, // no StringCharAt
- kNoReduction = 1 << 9, // no reduction
- kNoSAD = 1 << 10, // no sum of absolute differences (SAD)
- kNoWideSAD = 1 << 11, // no sum of absolute differences (SAD) with operand widening
- kNoDotProd = 1 << 12, // no dot product
+ kNoUnsignedHAdd = 1 << 6, // no unsigned halving add
+ kNoUnroundedHAdd = 1 << 7, // no unrounded halving add
+ kNoAbs = 1 << 8, // no absolute value
+ kNoStringCharAt = 1 << 9, // no StringCharAt
+ kNoReduction = 1 << 10, // no reduction
+ kNoSAD = 1 << 11, // no sum of absolute differences (SAD)
+ kNoWideSAD = 1 << 12, // no sum of absolute differences (SAD) with operand widening
+ kNoDotProd = 1 << 13, // no dot product
};
/*
@@ -270,6 +271,8 @@
void RemoveDeadInstructions(const HInstructionList& list);
bool CanRemoveCycle(); // Whether the current 'iset_' is removable.
+ bool IsInPredicatedVectorizationMode() const { return predicated_vectorization_mode_; }
+
// Compiler options (to query ISA features).
const CompilerOptions* compiler_options_;
@@ -305,6 +308,9 @@
// Flag that tracks if any simplifications have occurred.
bool simplified_;
+ // Whether to use predicated loop vectorization (e.g. for arm64 SVE target).
+ bool predicated_vectorization_mode_;
+
// Number of "lanes" for selected packed type.
uint32_t vector_length_;