ART: Implement predicated SIMD vectorization.
This CL brings support for predicated execution for
auto-vectorizer and implements arm64 SVE vector backend.
This version passes all the VIXL simulator-runnable tests in
SVE mode with checker off (as all VecOp CHECKs need to be
adjusted for an extra input) and all tests in NEON mode.
Test: art SIMD tests on VIXL simulator.
Test: art tests on FVP (steps in test/README.arm_fvp.md)
Change-Id: Ib78bde31a15e6713d875d6668ad4458f5519605f
diff --git a/compiler/optimizing/code_generator_arm64.h b/compiler/optimizing/code_generator_arm64.h
index affc640..eb3e954 100644
--- a/compiler/optimizing/code_generator_arm64.h
+++ b/compiler/optimizing/code_generator_arm64.h
@@ -54,9 +54,6 @@
static constexpr int kMaxMacroInstructionSizeInBytes = 15 * vixl::aarch64::kInstructionSize;
static constexpr int kInvokeCodeMarginSizeInBytes = 6 * kMaxMacroInstructionSizeInBytes;
-// SVE is currently not enabled.
-static constexpr bool kArm64AllowSVE = false;
-
static const vixl::aarch64::Register kParameterCoreRegisters[] = {
vixl::aarch64::x1,
vixl::aarch64::x2,
@@ -388,11 +385,19 @@
void GenerateIntRemForPower2Denom(HRem *instruction);
void HandleGoto(HInstruction* got, HBasicBlock* successor);
- // Helper to set up locations for vector memory operations. Returns the memory operand and,
+ // Helpers to set up locations for vector memory operations. Returns the memory operand and,
// if used, sets the output parameter scratch to a temporary register used in this operand,
// so that the client can release it right after the memory operand use.
// Neon version.
- vixl::aarch64::MemOperand VecNeonAddress(
+ vixl::aarch64::MemOperand VecNEONAddress(
+ HVecMemoryOperation* instruction,
+ // This function may acquire a scratch register.
+ vixl::aarch64::UseScratchRegisterScope* temps_scope,
+ size_t size,
+ bool is_string_char_at,
+ /*out*/ vixl::aarch64::Register* scratch);
+ // SVE version.
+ vixl::aarch64::SVEMemOperand VecSVEAddress(
HVecMemoryOperation* instruction,
// This function may acquire a scratch register.
vixl::aarch64::UseScratchRegisterScope* temps_scope,
@@ -490,6 +495,15 @@
void LoadSIMDRegFromStack(Location destination, Location source) override;
void MoveSIMDRegToSIMDReg(Location destination, Location source) override;
void MoveToSIMDStackSlot(Location destination, Location source) override;
+
+ private:
+ // Returns default predicate register which is used as governing vector predicate
+ // to implement predicated loop execution.
+ //
+ // TODO: This is a hack to be addressed when register allocator supports SIMD types.
+ static vixl::aarch64::PRegister LoopPReg() {
+ return vixl::aarch64::p0;
+ }
};
class LocationsBuilderARM64Sve : public LocationsBuilderARM64 {