commit 8ba4de1a5684686447a578bdc425321fd3bccca6
author Artem Serov <artem.serov@linaro.org> Wed Dec 04 21:10:23 2019 +0000
committer Ulyana Trafimovich <skvadrik@google.com> Thu Feb 04 06:16:33 2021 +0000
tree 20c24450b24950266ccc235306e3ad2109c57497
parent 32bf6d39bc020cacfc655ce60630f4a0da3b45cf

ART: Implement predicated SIMD vectorization.

This CL brings support for predicated execution for
auto-vectorizer and implements arm64 SVE vector backend.

This version passes all the VIXL simulator-runnable tests in
SVE mode with checker off (as all VecOp CHECKs need to be
adjusted for an extra input) and all tests in NEON mode.

Test: art SIMD tests on VIXL simulator.
Test: art tests on FVP (steps in test/README.arm_fvp.md)

Change-Id: Ib78bde31a15e6713d875d6668ad4458f5519605f

compiler/optimizing/code_generator_arm64.cc

diff --git a/compiler/optimizing/code_generator_arm64.cc b/compiler/optimizing/code_generator_arm64.cc
index b945be2..f5d7836 100644
--- a/compiler/optimizing/code_generator_arm64.cc
+++ b/compiler/optimizing/code_generator_arm64.cc
@@ -994,7 +994,7 @@
 }
 
 bool CodeGeneratorARM64::ShouldUseSVE() const {
-  return kArm64AllowSVE && GetInstructionSetFeatures().HasSVE();
+  return GetInstructionSetFeatures().HasSVE();
 }
 
 #define __ GetVIXLAssembler()->
@@ -6908,7 +6908,7 @@
   }
 }
 
-MemOperand InstructionCodeGeneratorARM64::VecNeonAddress(
+MemOperand InstructionCodeGeneratorARM64::VecNEONAddress(
     HVecMemoryOperation* instruction,
     UseScratchRegisterScope* temps_scope,
     size_t size,
@@ -6941,6 +6941,31 @@
   }
 }
 
+SVEMemOperand InstructionCodeGeneratorARM64::VecSVEAddress(
+    HVecMemoryOperation* instruction,
+    UseScratchRegisterScope* temps_scope,
+    size_t size,
+    bool is_string_char_at,
+    /*out*/ Register* scratch) {
+  LocationSummary* locations = instruction->GetLocations();
+  Register base = InputRegisterAt(instruction, 0);
+  Location index = locations->InAt(1);
+
+  // TODO: Support intermediate address sharing for SVE accesses.
+  DCHECK(!instruction->InputAt(1)->IsIntermediateAddressIndex());
+  DCHECK(!instruction->InputAt(0)->IsIntermediateAddress());
+  DCHECK(!index.IsConstant());
+
+  uint32_t offset = is_string_char_at
+      ? mirror::String::ValueOffset().Uint32Value()
+      : mirror::Array::DataOffset(size).Uint32Value();
+  size_t shift = ComponentSizeShiftWidth(size);
+
+  *scratch = temps_scope->AcquireSameSizeAs(base);
+  __ Add(*scratch, base, offset);
+  return SVEMemOperand(scratch->X(), XRegisterFrom(index), LSL, shift);
+}
+
 #undef __
 #undef QUICK_ENTRY_POINT