commit 88ccd92e57804ed958dec9da0fc8b67b924b3db7
author Lokesh Gidra <lokeshgidra@google.com> Wed Sep 28 23:23:43 2022 -0700
committer Lokesh Gidra <lokeshgidra@google.com> Thu Sep 29 15:25:58 2022 +0000
tree 27a64f02cd5377f1fb7c9bf0ec83e793700045e2
parent 3a60d011496dd5281410ee416b8b82cb94f4f599

Make callee-saved registers behave according to kReserveMarkingRegister

We were mistakenly blocking the marking register and refreshing it, but
didn't remove it from callee-saved registers list when CC GC is not
being used, leading to crashes.

Test: art/test/testrnunner/testrunner.py --target --32 --jit
Change-Id: I33e18c900042fd1dfb1f75512868c895fd83c1e1

compiler/optimizing/code_generator_arm_vixl.h

diff --git a/compiler/optimizing/code_generator_arm_vixl.h b/compiler/optimizing/code_generator_arm_vixl.h
index fc5fc48..e5b31cf 100644
--- a/compiler/optimizing/code_generator_arm_vixl.h
+++ b/compiler/optimizing/code_generator_arm_vixl.h
@@ -84,7 +84,7 @@
                                 vixl::aarch32::r6,
                                 vixl::aarch32::r7),
     // Do not consider r8 as a callee-save register with Baker read barriers.
-    ((gUseReadBarrier && kUseBakerReadBarrier)
+    (kReserveMarkingRegister
          ? vixl::aarch32::RegisterList()
          : vixl::aarch32::RegisterList(vixl::aarch32::r8)),
     vixl::aarch32::RegisterList(vixl::aarch32::r10,