Quick compiler: generalize NarrowRegLoc()
Some of the RegStorage utilites (DoubleToLowSingle(),
DoubleToHighSingle(), etc.) worked only for targets which
which treat double precision registers as a pair of aliased
single precision registers.
This CL elminates those utilities, and replaces them with
a new RegisterInfo utility that will search an aliased register
set and return the member matching the required storage
configuration (if it exists).
Change-Id: Iff5de10f467d20a56e1a89df9fbf30d1cf63c240
diff --git a/compiler/dex/quick/codegen_util.cc b/compiler/dex/quick/codegen_util.cc
index 256135d..3fbbc4e 100644
--- a/compiler/dex/quick/codegen_util.cc
+++ b/compiler/dex/quick/codegen_util.cc
@@ -1201,21 +1201,27 @@
}
RegLocation Mir2Lir::NarrowRegLoc(RegLocation loc) {
- loc.wide = false;
if (loc.location == kLocPhysReg) {
+ DCHECK(!loc.reg.Is32Bit());
if (loc.reg.IsPair()) {
- loc.reg = loc.reg.GetLow();
+ RegisterInfo* info_lo = GetRegInfo(loc.reg.GetLow());
+ RegisterInfo* info_hi = GetRegInfo(loc.reg.GetHigh());
+ info_lo->SetIsWide(false);
+ info_hi->SetIsWide(false);
+ loc.reg = info_lo->GetReg();
} else {
- // FIXME: temp workaround.
- // Issue here: how do we narrow to a 32-bit value in 64-bit container?
- // Probably the wrong thing to narrow the RegStorage container here. That
- // should be a target decision. At the RegLocation level, we're only
- // modifying the view of the Dalvik value - this is orthogonal to the storage
- // container size. Consider this a temp workaround.
- DCHECK(loc.reg.IsDouble());
- loc.reg = loc.reg.DoubleToLowSingle();
+ RegisterInfo* info = GetRegInfo(loc.reg);
+ RegisterInfo* info_new = info->FindMatchingView(RegisterInfo::k32SoloStorageMask);
+ DCHECK(info_new != nullptr);
+ if (info->IsLive() && (info->SReg() == loc.s_reg_low)) {
+ info->MarkDead();
+ info_new->MarkLive(loc.s_reg_low);
+ }
+ loc.reg = info_new->GetReg();
}
+ DCHECK(loc.reg.Valid());
}
+ loc.wide = false;
return loc;
}