commit 79db99711f6b27f6ced6b7ed52c827f5211010a9
author Scott Wakeling <scott.wakeling@linaro.org> Thu Jan 19 14:08:42 2017 +0000
committer Scott Wakeling <scott.wakeling@linaro.org> Fri Jan 27 10:17:44 2017 +0000
tree f153b68f97eaa8f71e87f5978b82112544af0acf
parent e36c51aee58e61e9fc89851b767379c587f050e3

ARM64: VIXL: Fix breaking changes to ternary operator with Register inputs.

Test: mma art
Change-Id: I33d1e05e47f337f1a9271b35dba9227057cda096

compiler/optimizing/code_generator_arm64.cc

diff --git a/compiler/optimizing/code_generator_arm64.cc b/compiler/optimizing/code_generator_arm64.cc
index 9762ee8..368c543 100644
--- a/compiler/optimizing/code_generator_arm64.cc
+++ b/compiler/optimizing/code_generator_arm64.cc
@@ -1533,7 +1533,9 @@
       HConstant* src_cst = source.GetConstant();
       CPURegister temp;
       if (src_cst->IsZeroBitPattern()) {
-        temp = (src_cst->IsLongConstant() || src_cst->IsDoubleConstant()) ? xzr : wzr;
+        temp = (src_cst->IsLongConstant() || src_cst->IsDoubleConstant())
+            ? Register(xzr)
+            : Register(wzr);
       } else {
         if (src_cst->IsIntConstant()) {
           temp = temps.AcquireW();