commit 7793404935f70bc6dfffba316f5e5588f38979b5
author George Burgess IV <gbiv@google.com> Mon Aug 13 10:59:31 2018 -0700
committer George Burgess IV <gbiv@google.com> Mon Aug 13 11:00:44 2018 -0700
tree 1f4dd42932b0a019a8e61bdd1bff9087df6733d9
parent d55446b7c62acaecf01f4ffd03d8a0d0b0f4e448

veridex: fix a sketchy switch scope

Should be harmless, but it tripped me up when trying to read this code.

Bug: None
Test: Treehugger
Change-Id: Iefa56768d9625a3f67e2ee377040808576ffc625

tools/veridex/flow_analysis.cc

diff --git a/tools/veridex/flow_analysis.cc b/tools/veridex/flow_analysis.cc
index f5eb4ea..69f7def 100644
--- a/tools/veridex/flow_analysis.cc
+++ b/tools/veridex/flow_analysis.cc
@@ -495,7 +495,7 @@
     case Instruction::DIV_INT_LIT8:
     case Instruction::REM_INT_LIT8:
     case Instruction::SHL_INT_LIT8:
-    case Instruction::SHR_INT_LIT8: {
+    case Instruction::SHR_INT_LIT8:
     case Instruction::USHR_INT_LIT8: {
       UpdateRegister(instruction.VRegA(), VeriClass::integer_);
       break;
@@ -537,7 +537,7 @@
     case Instruction::CMPG_FLOAT:
     case Instruction::CMPG_DOUBLE:
     case Instruction::CMPL_FLOAT:
-    case Instruction::CMPL_DOUBLE:
+    case Instruction::CMPL_DOUBLE: {
       UpdateRegister(instruction.VRegA(), VeriClass::integer_);
       break;
     }