Opt Compiler: ARM64 goodness
This patch:
* Switches on PreferAcquireRelease() (used to decide if load/store
volatile should use acquire release-semantics or explicit memory
barriers). Note that for ARMv8 CPUs we should always prefer this
(as proved by synthetic benchmarks on A53, A57 and Denver).
* Enables the use of constants for HBoundsCheck
Change-Id: I42524451772c05a1c74af73e97a59a95f49ba6d4
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
diff --git a/compiler/optimizing/code_generator_arm64.cc b/compiler/optimizing/code_generator_arm64.cc
index ee04b3a..caf7cc7 100644
--- a/compiler/optimizing/code_generator_arm64.cc
+++ b/compiler/optimizing/code_generator_arm64.cc
@@ -1333,7 +1333,7 @@
LocationSummary* locations =
new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kNoCall);
locations->SetInAt(0, Location::RequiresRegister());
- locations->SetInAt(1, Location::RequiresRegister());
+ locations->SetInAt(1, ARM64EncodableConstantOrRegister(instruction->InputAt(1), instruction));
if (instruction->HasUses()) {
locations->SetOut(Location::SameAsFirstInput());
}
diff --git a/compiler/optimizing/common_arm64.h b/compiler/optimizing/common_arm64.h
index 966165b..53f1f3c 100644
--- a/compiler/optimizing/common_arm64.h
+++ b/compiler/optimizing/common_arm64.h
@@ -194,7 +194,8 @@
int64_t value = CodeGenerator::GetInt64ValueOf(constant);
- if (instr->IsAdd() || instr->IsSub() || instr->IsCondition() || instr->IsCompare()) {
+ if (instr->IsAdd() || instr->IsSub() || instr->IsCondition() ||
+ instr->IsCompare() || instr->IsBoundsCheck()) {
// Uses aliases of ADD/SUB instructions.
return vixl::Assembler::IsImmAddSub(value);
} else if (instr->IsAnd() || instr->IsOr() || instr->IsXor()) {
diff --git a/runtime/arch/arm64/instruction_set_features_arm64.h b/runtime/arch/arm64/instruction_set_features_arm64.h
index 3b3e2c9..e59ff58 100644
--- a/runtime/arch/arm64/instruction_set_features_arm64.h
+++ b/runtime/arch/arm64/instruction_set_features_arm64.h
@@ -66,13 +66,12 @@
return fix_cortex_a53_843419_;
}
- // TODO: Tune this on a per CPU basis. For now, we pessimistically assume
- // that all ARM64 CPUs prefer explicit memory barriers over acquire-release.
- //
- // NOTE: This should not be the case! However we want to exercise the
- // explicit memory barriers code paths in the Optimizing Compiler.
+ // NOTE: This flag can be tunned on a CPU basis. In general all ARMv8 CPUs
+ // should prefer the Acquire-Release semantics over the explicit DMBs when
+ // handling load/store-volatile. For a specific use case see the ARM64
+ // Optimizing backend.
bool PreferAcquireRelease() const {
- return false;
+ return true;
}
virtual ~Arm64InstructionSetFeatures() {}
diff --git a/runtime/arch/arm64/instruction_set_features_arm64_test.cc b/runtime/arch/arm64/instruction_set_features_arm64_test.cc
index 753107b..599f24e 100644
--- a/runtime/arch/arm64/instruction_set_features_arm64_test.cc
+++ b/runtime/arch/arm64/instruction_set_features_arm64_test.cc
@@ -31,7 +31,7 @@
EXPECT_STREQ("smp,a53", arm64_features->GetFeatureString().c_str());
EXPECT_EQ(arm64_features->AsBitmap(), 3U);
// See the comments in instruction_set_features_arm64.h.
- EXPECT_FALSE(arm64_features->AsArm64InstructionSetFeatures()->PreferAcquireRelease());
+ EXPECT_TRUE(arm64_features->AsArm64InstructionSetFeatures()->PreferAcquireRelease());
}
} // namespace art