Stop saying "typedef struct" and "typedef enum".
Seeing new instances of this C-ism go in makes me a sad panda.
Change-Id: Ie3dd414b8b5e57a4164e88eb2d8559545569628d
diff --git a/jdwpspy/Common.h b/jdwpspy/Common.h
index f942dee..0bd3056 100644
--- a/jdwpspy/Common.h
+++ b/jdwpspy/Common.h
@@ -93,7 +93,7 @@
* "mem" mode shows the actual memory address, and will offset the start
* so that the low nibble of the address is always zero.
*/
-typedef enum { kHexDumpLocal, kHexDumpMem } HexDumpMode;
+enum HexDumpMode { kHexDumpLocal, kHexDumpMem };
void printHexDump(const void* vaddr, size_t length);
void printHexDump2(const void* vaddr, size_t length, const char* prefix);
void printHexDumpEx(FILE* fp, const void* vaddr, size_t length,
diff --git a/jdwpspy/Net.cpp b/jdwpspy/Net.cpp
index 209cf28..abcae21 100644
--- a/jdwpspy/Net.cpp
+++ b/jdwpspy/Net.cpp
@@ -33,7 +33,7 @@
/*
* Information about the remote end.
*/
-typedef struct Peer {
+struct Peer {
char label[2]; /* 'D' or 'V' */
int sock;
@@ -41,13 +41,13 @@
int inputCount;
bool awaitingHandshake; /* waiting for "JDWP-Handshake" */
-} Peer;
+};
/*
* Network state.
*/
-typedef struct NetState {
+struct NetState {
/* listen here for connection from debugger */
int listenSock;
@@ -57,16 +57,16 @@
Peer dbg;
Peer vm;
-} NetState;
+};
/*
* Function names.
*/
-typedef struct {
+struct JdwpHandlerMap {
u1 cmdSet;
u1 cmd;
const char* descr;
-} JdwpHandlerMap;
+};
/*
* Map commands to names.
diff --git a/src/compiler/Compiler.h b/src/compiler/Compiler.h
index 8636e11..a457fa6 100644
--- a/src/compiler/Compiler.h
+++ b/src/compiler/Compiler.h
@@ -135,7 +135,7 @@
/* Flips sense of compilerMethodMatch - apply flags if doesn't match */
extern bool compilerFlipMatch;
-typedef enum OatMethodAttributes {
+enum OatMethodAttributes {
kIsCallee = 0, /* Code is part of a callee (invoked by a hot trace) */
kIsHot, /* Code is part of a hot trace */
kIsLeaf, /* Method is leaf */
@@ -144,7 +144,7 @@
kIsGetter, /* Method fits the getter pattern */
kIsSetter, /* Method fits the setter pattern */
kCannotCompile, /* Method cannot be compiled */
-} OatMethodAttributes;
+};
#define METHOD_IS_CALLEE (1 << kIsCallee)
#define METHOD_IS_HOT (1 << kIsHot)
@@ -156,14 +156,14 @@
#define METHOD_CANNOT_COMPILE (1 << kCannotCompile)
/* Customized node traversal orders for different needs */
-typedef enum DataFlowAnalysisMode {
+enum DataFlowAnalysisMode {
kAllNodes = 0, // All nodes
kReachableNodes, // All reachable nodes
kPreOrderDFSTraversal, // Depth-First-Search / Pre-Order
kPostOrderDFSTraversal, // Depth-First-Search / Post-Order
kPostOrderDOMTraversal, // Dominator tree / Post-Order
kReversePostOrderTraversal, // Depth-First-Search / reverse Post-Order
-} DataFlowAnalysisMode;
+};
struct CompilationUnit;
struct BasicBlock;
diff --git a/src/compiler/CompilerIR.h b/src/compiler/CompilerIR.h
index 2515713..c6d14c3 100644
--- a/src/compiler/CompilerIR.h
+++ b/src/compiler/CompilerIR.h
@@ -35,27 +35,27 @@
#define EXERCISE_RESOLVE_METHOD (cUnit->enableDebug & \
(1 << kDebugExerciseResolveMethod))
-typedef enum RegisterClass {
+enum RegisterClass {
kCoreReg,
kFPReg,
kAnyReg,
-} RegisterClass;
+};
-typedef enum RegLocationType {
+enum RegLocationType {
kLocDalvikFrame = 0, // Normal Dalvik register
kLocPhysReg,
kLocSpill,
-} RegLocationType;
+};
-typedef struct PromotionMap {
+struct PromotionMap {
RegLocationType coreLocation:3;
u1 coreReg;
RegLocationType fpLocation:3;
u1 fpReg;
bool firstInPair;
-} PromotionMap;
+};
-typedef struct RegLocation {
+struct RegLocation {
RegLocationType location:3;
unsigned wide:1;
unsigned defined:1; // Do we know the type?
@@ -66,7 +66,7 @@
u1 lowReg; // First physical register
u1 highReg; // 2nd physical register (if wide)
s2 sRegLow; // SSA name for low Dalvik word
-} RegLocation;
+};
/*
* Data structure tracking the mapping between a Dalvik register (pair) and a
@@ -74,7 +74,7 @@
* if possible, otherwise to keep the value in a native register as long as
* possible.
*/
-typedef struct RegisterInfo {
+struct RegisterInfo {
int reg; // Reg number
bool inUse; // Has it been allocated?
bool isTemp; // Can allocate as temp?
@@ -85,16 +85,16 @@
int sReg; // Name of live value
struct LIR *defStart; // Starting inst in last def sequence
struct LIR *defEnd; // Ending inst in last def sequence
-} RegisterInfo;
+};
-typedef struct RegisterPool {
+struct RegisterPool {
int numCoreRegs;
RegisterInfo *coreRegs;
int nextCoreReg;
int numFPRegs;
RegisterInfo *FPRegs;
int nextFPReg;
-} RegisterPool;
+};
#define INVALID_SREG (-1)
#define INVALID_VREG (0xFFFFU)
@@ -112,13 +112,13 @@
#define MANY_BLOCKS_INITIALIZER 1000 /* Threshold for switching dataflow off */
#define MANY_BLOCKS 4000 /* Non-initializer threshold */
-typedef enum BBType {
+enum BBType {
kEntryBlock,
kDalvikByteCode,
kExitBlock,
kExceptionHandling,
kCatchEntry,
-} BBType;
+};
/* Utility macros to traverse the LIR list */
#define NEXT_LIR(lir) (lir->next)
@@ -127,7 +127,7 @@
#define NEXT_LIR_LVALUE(lir) (lir)->next
#define PREV_LIR_LVALUE(lir) (lir)->prev
-typedef struct LIR {
+struct LIR {
int offset; // Offset of this instruction
int dalvikOffset; // Offset of Dalvik opcode
struct LIR* next;
@@ -145,7 +145,7 @@
int aliasInfo; // For Dalvik register & litpool disambiguation
u8 useMask; // Resource mask for use
u8 defMask; // Resource mask for def
-} LIR;
+};
enum ExtendedMIROpcode {
kMirOpFirst = kNumPackedOpcodes,
@@ -160,7 +160,7 @@
struct SSARepresentation;
-typedef enum {
+enum MIROptimizationFlagPositons {
kMIRIgnoreNullCheck = 0,
kMIRNullCheckOnly,
kMIRIgnoreRangeCheck,
@@ -169,7 +169,7 @@
kMIRInlinedPred, // Invoke is inlined via prediction
kMIRCallee, // Instruction is inlined from callee
kMIRIgnoreSuspendCheck,
-} MIROptimizationFlagPositons;
+};
#define MIR_IGNORE_NULL_CHECK (1 << kMIRIgnoreNullCheck)
#define MIR_NULL_CHECK_ONLY (1 << kMIRNullCheckOnly)
@@ -180,14 +180,14 @@
#define MIR_CALLEE (1 << kMIRCallee)
#define MIR_IGNORE_SUSPEND_CHECK (1 << kMIRIgnoreSuspendCheck)
-typedef struct CallsiteInfo {
+struct CallsiteInfo {
const char* classDescriptor;
Object* classLoader;
const Method* method;
LIR* misPredBranchOver;
-} CallsiteInfo;
+};
-typedef struct MIR {
+struct MIR {
DecodedInstruction dalvikInsn;
unsigned int width;
unsigned int offset;
@@ -204,19 +204,19 @@
// Used to quickly locate all Phi opcodes
struct MIR* phiNext;
} meta;
-} MIR;
+};
struct BasicBlockDataFlow;
/* For successorBlockList */
-typedef enum BlockListType {
+enum BlockListType {
kNotUsed = 0,
kCatch,
kPackedSwitch,
kSparseSwitch,
-} BlockListType;
+};
-typedef struct BasicBlock {
+struct BasicBlock {
int id;
int dfsId;
bool visited;
@@ -241,7 +241,7 @@
BlockListType blockListType; // switch and exception handling
GrowableList blocks;
} successorBlockList;
-} BasicBlock;
+};
/*
* The "blocks" field in "successorBlockList" points to an array of
@@ -249,25 +249,25 @@
* For catch blocks, key is type index for the exception.
* For swtich blocks, key is the case value.
*/
-typedef struct SuccessorBlockInfo {
+struct SuccessorBlockInfo {
BasicBlock* block;
int key;
-} SuccessorBlockInfo;
+};
struct LoopAnalysis;
struct RegisterPool;
struct ArenaMemBlock;
struct Memstats;
-typedef enum AssemblerStatus {
+enum AssemblerStatus {
kSuccess,
kRetryAll,
kRetryHalve
-} AssemblerStatus;
+};
#define NOTVISITED (-1)
-typedef struct CompilationUnit {
+struct CompilationUnit {
int numInsts;
int numBlocks;
GrowableList blockList;
@@ -399,9 +399,9 @@
struct ArenaMemBlock* currentArena;
int numArenaBlocks;
struct Memstats* mstats;
-} CompilationUnit;
+};
-typedef enum OpSize {
+enum OpSize {
kWord,
kLong,
kSingle,
@@ -410,9 +410,9 @@
kSignedHalf,
kUnsignedByte,
kSignedByte,
-} OpSize;
+};
-typedef enum OpKind {
+enum OpKind {
kOpMov,
kOpMvn,
kOpCmp,
@@ -447,11 +447,11 @@
kOpUncondBr,
kOpBx,
kOpInvalid,
-} OpKind;
+};
std::ostream& operator<<(std::ostream& os, const OpKind& kind);
-typedef enum ConditionCode {
+enum ConditionCode {
kCondEq,
kCondNe,
kCondCs,
@@ -468,9 +468,9 @@
kCondLe,
kCondAl,
kCondNv,
-} ConditionCode;
+};
-typedef enum ThrowKind {
+enum ThrowKind {
kThrowNullPointer,
kThrowDivZero,
kThrowArrayBounds,
@@ -478,22 +478,22 @@
kThrowNegArraySize,
kThrowNoSuchMethod,
kThrowStackOverflow,
-} ThrowKind;
+};
-typedef struct SwitchTable {
+struct SwitchTable {
int offset;
const u2* table; // Original dex table
int vaddr; // Dalvik offset of switch opcode
LIR* anchor; // Reference instruction for relative offsets
LIR** targets; // Array of case targets
-} SwitchTable;
+};
-typedef struct FillArrayData {
+struct FillArrayData {
int offset;
const u2* table; // Original dex table
int size;
int vaddr; // Dalvik offset of FILL_ARRAY_DATA opcode
-} FillArrayData;
+};
BasicBlock* oatNewBB(CompilationUnit* cUnit, BBType blockType, int blockId);
diff --git a/src/compiler/CompilerUtility.h b/src/compiler/CompilerUtility.h
index a6ddd1e..357fe51 100644
--- a/src/compiler/CompilerUtility.h
+++ b/src/compiler/CompilerUtility.h
@@ -30,32 +30,32 @@
/* Collect memory usage statstics */
//#define WITH_MEMSTATS
-typedef struct ArenaMemBlock {
+struct ArenaMemBlock {
size_t blockSize;
size_t bytesAllocated;
struct ArenaMemBlock *next;
char ptr[0];
-} ArenaMemBlock;
+};
void* oatNew(CompilationUnit* cUnit, size_t size, bool zero,
oatAllocKind kind = kAllocMisc);
void oatArenaReset(CompilationUnit *cUnit);
-typedef struct GrowableList {
+struct GrowableList {
size_t numAllocated;
size_t numUsed;
intptr_t *elemList;
#ifdef WITH_MEMSTATS
oatListKind kind;
#endif
-} GrowableList;
+};
-typedef struct GrowableListIterator {
+struct GrowableListIterator {
GrowableList* list;
size_t idx;
size_t size;
-} GrowableListIterator;
+};
/*
* Expanding bitmap, used for tracking resources. Bits are numbered starting
diff --git a/src/compiler/Dataflow.h b/src/compiler/Dataflow.h
index 22a03b7..a9917a3 100644
--- a/src/compiler/Dataflow.h
+++ b/src/compiler/Dataflow.h
@@ -22,7 +22,7 @@
namespace art {
-typedef enum DataFlowAttributePos {
+enum DataFlowAttributePos {
kUA = 0,
kUB,
kUC,
@@ -54,7 +54,7 @@
kCoreC,
kGetter,
kSetter,
-} DataFlowAttributes;
+};
#define DF_NOP 0
#define DF_UA (1 << kUA)
@@ -110,42 +110,42 @@
extern const int oatDataFlowAttributes[kMirOpLast];
-typedef struct BasicBlockDataFlow {
+struct BasicBlockDataFlow {
ArenaBitVector* useV;
ArenaBitVector* defV;
ArenaBitVector* liveInV;
ArenaBitVector* phiV;
int* dalvikToSSAMap;
ArenaBitVector* endingNullCheckV;
-} BasicBlockDataFlow;
+};
-typedef struct SSARepresentation {
+struct SSARepresentation {
int numUses;
int* uses;
bool* fpUse;
int numDefs;
int* defs;
bool* fpDef;
-} SSARepresentation;
+};
/*
* An induction variable is represented by "m*i + c", where i is a basic
* induction variable.
*/
-typedef struct InductionVariableInfo {
+struct InductionVariableInfo {
int ssaReg;
int basicSSAReg;
int m; // multiplier
int c; // constant
int inc; // loop increment
-} InductionVariableInfo;
+};
-typedef struct ArrayAccessInfo {
+struct ArrayAccessInfo {
int arrayReg;
int ivReg;
int maxC; // For DIV - will affect upper bound checking
int minC; // For DIV - will affect lower bound checking
-} ArrayAccessInfo;
+};
#define ENCODE_REG_SUB(r,s) ((s<<16) | r)
#define DECODE_REG(v) (v & 0xffff)
diff --git a/src/compiler/Utility.cc b/src/compiler/Utility.cc
index f86b72c..082f7a4 100644
--- a/src/compiler/Utility.cc
+++ b/src/compiler/Utility.cc
@@ -20,7 +20,7 @@
namespace art {
#ifdef WITH_MEMSTATS
-typedef struct Memstats {
+struct Memstats {
u4 allocStats[kNumAllocKinds];
int listSizes[kNumListKinds];
int listWasted[kNumListKinds];
@@ -29,7 +29,7 @@
int bitMapSizes[kNumBitMapKinds];
int bitMapWasted[kNumBitMapKinds];
int bitMapGrows[kNumBitMapKinds];
-} memstats;
+};
const char* allocNames[kNumAllocKinds] = {
"Misc ",
diff --git a/src/compiler/codegen/Ralloc.h b/src/compiler/codegen/Ralloc.h
index c9e5308..8c8c693 100644
--- a/src/compiler/codegen/Ralloc.h
+++ b/src/compiler/codegen/Ralloc.h
@@ -28,11 +28,11 @@
namespace art {
/* Static register use counts */
-typedef struct RefCounts {
+struct RefCounts {
int count;
int sReg;
bool doubleStart; // Starting vReg for a double
-} RefCounts;
+};
inline int oatS2VReg(CompilationUnit* cUnit, int sReg)
diff --git a/src/compiler/codegen/arm/ArmLIR.h b/src/compiler/codegen/arm/ArmLIR.h
index bc85dd8..2f332f5 100644
--- a/src/compiler/codegen/arm/ArmLIR.h
+++ b/src/compiler/codegen/arm/ArmLIR.h
@@ -129,7 +129,7 @@
INVALID_SREG}
#define LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG}
-typedef enum ResourceEncodingPos {
+enum ResourceEncodingPos {
kGPReg0 = 0,
kRegSP = 13,
kRegLR = 14,
@@ -144,7 +144,7 @@
kLiteral, // 2 Literal pool (can be fully disambiguated)
kHeapRef, // 3 Somewhere on the heap (alias with any other heap)
kMustNotAlias, // 4 Guaranteed to be non-alias (eg *(r6+x))
-} ResourceEncodingPos;
+};
#define ENCODE_REG_LIST(N) ((u8) N)
#define ENCODE_REG_SP (1ULL << kRegSP)
@@ -174,7 +174,7 @@
*
* rPC, rFP, and rSELF are for architecture-independent code to use.
*/
-typedef enum NativeRegisterPool {
+enum NativeRegisterPool {
r0 = 0,
r1 = 1,
r2 = 2,
@@ -242,7 +242,7 @@
dr13 = fr26 + FP_DOUBLE,
dr14 = fr28 + FP_DOUBLE,
dr15 = fr30 + FP_DOUBLE,
-} NativeRegisterPool;
+};
/* Target-independent aliases */
#define rARG0 r0
@@ -254,15 +254,15 @@
#define rINVOKE_TGT rLR
/* Shift encodings */
-typedef enum ArmShiftEncodings {
+enum ArmShiftEncodings {
kArmLsl = 0x0,
kArmLsr = 0x1,
kArmAsr = 0x2,
kArmRor = 0x3
-} ArmShiftEncodings;
+};
/* Thumb condition encodings */
-typedef enum ArmConditionCode {
+enum ArmConditionCode {
kArmCondEq = 0x0, /* 0000 */
kArmCondNe = 0x1, /* 0001 */
kArmCondCs = 0x2, /* 0010 */
@@ -279,7 +279,7 @@
kArmCondLe = 0xd, /* 1101 */
kArmCondAl = 0xe, /* 1110 */
kArmCondNv = 0xf, /* 1111 */
-} ArmConditionCode;
+};
#define isPseudoOpcode(opcode) ((int)(opcode) < 0)
@@ -288,7 +288,7 @@
* assembler. Their corresponding EncodingMap positions will be defined in
* Assemble.cc.
*/
-typedef enum ArmOpcode {
+enum ArmOpcode {
kPseudoSuspendTarget = -15,
kPseudoThrowTarget = -14,
kPseudoCaseLabel = -13,
@@ -616,20 +616,20 @@
kThumb2Push1, /* t3 encoding of push */
kThumb2Pop1, /* t3 encoding of pop */
kArmLast,
-} ArmOpcode;
+};
/* DMB option encodings */
-typedef enum ArmOpDmbOptions {
+enum ArmOpDmbOptions {
kSY = 0xf,
kST = 0xe,
kISH = 0xb,
kISHST = 0xa,
kNSH = 0x7,
kNSHST = 0x6
-} ArmOpDmbOptions;
+};
/* Bit flags describing the behavior of each native opcode */
-typedef enum ArmOpFeatureFlags {
+enum ArmOpFeatureFlags {
kIsBranch = 0,
kRegDef0,
kRegDef1,
@@ -661,7 +661,7 @@
kMemLoad,
kMemStore,
kPCRelFixup,
-} ArmOpFeatureFlags;
+};
#define IS_LOAD (1 << kMemLoad)
#define IS_STORE (1 << kMemStore)
@@ -705,7 +705,7 @@
#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2)
/* Instruction assembly fieldLoc kind */
-typedef enum ArmEncodingKind {
+enum ArmEncodingKind {
kFmtUnused,
kFmtBitBlt, /* Bit string using end/start */
kFmtDfp, /* Double FP reg */
@@ -721,10 +721,10 @@
kFmtBrOffset, /* Signed extended [26,11,13,21-16,10-0]:0 */
kFmtFPImm, /* Encoded floating point immediate */
kFmtOff24, /* 24-bit Thumb2 unconditional branch encoding */
-} ArmEncodingKind;
+};
/* Struct used to define the snippet positions for each Thumb opcode */
-typedef struct ArmEncodingMap {
+struct ArmEncodingMap {
u4 skeleton;
struct {
ArmEncodingKind kind;
@@ -736,12 +736,12 @@
const char* name;
const char* fmt;
int size; /* Size in bytes */
-} ArmEncodingMap;
+};
/* Keys for target-specific scheduling and other optimization hints */
-typedef enum ArmTargetOptHints {
+enum ArmTargetOptHints {
kMaxHoistDistance,
-} ArmTargetOptHints;
+};
extern const ArmEncodingMap EncodingMap[kArmLast];
diff --git a/src/compiler/codegen/mips/MipsLIR.h b/src/compiler/codegen/mips/MipsLIR.h
index 341e56b..1e7a803 100644
--- a/src/compiler/codegen/mips/MipsLIR.h
+++ b/src/compiler/codegen/mips/MipsLIR.h
@@ -154,7 +154,7 @@
#define LOC_C_RETURN_WIDE_ALT {kLocPhysReg, 1, 0, 0, 0, 0, 1, r_FRESULT0,\
r_FRESULT1, INVALID_SREG}
-typedef enum ResourceEncodingPos {
+enum ResourceEncodingPos {
kGPReg0 = 0,
kRegSP = 29,
kRegLR = 31,
@@ -171,7 +171,7 @@
kLiteral, // 2 Literal pool (can be fully disambiguated)
kHeapRef, // 3 Somewhere on the heap (alias with any other heap)
kMustNotAlias, // 4 Guaranteed to be non-alias (eg *(r6+x))
-} ResourceEncodingPos;
+};
#define ENCODE_REG_LIST(N) ((u8) N)
#define ENCODE_REG_SP (1ULL << kRegSP)
@@ -197,7 +197,7 @@
* Annotate special-purpose core registers:
*/
-typedef enum NativeRegisterPool {
+enum NativeRegisterPool {
r_ZERO = 0,
r_AT = 1,
r_V0 = 2,
@@ -286,7 +286,7 @@
r_HI = EXTRA_REG_OFFSET,
r_LO,
r_PC,
-} NativeRegisterPool;
+};
/*
* Target-independent aliases
@@ -304,12 +304,12 @@
#define rINVOKE_TGT r_V0
/* Shift encodings */
-typedef enum MipsShiftEncodings {
+enum MipsShiftEncodings {
kMipsLsl = 0x0,
kMipsLsr = 0x1,
kMipsAsr = 0x2,
kMipsRor = 0x3
-} MipsShiftEncodings;
+};
// MIPS sync kinds (Note: support for kinds other than kSYNC0 may not exist)
#define kSYNC0 0x00
@@ -330,7 +330,7 @@
* assembler. Their corresponding EncodingMap positions will be defined in
* Assemble.cc.
*/
-typedef enum MipsOpCode {
+enum MipsOpCode {
kPseudoSuspendTarget = -15,
kPseudoThrowTarget = -14,
kPseudoCaseLabel = -13,
@@ -441,10 +441,10 @@
kMipsSync, /* sync kind [000000] [0000000000000000] s[10..6] [001111] */
kMipsUndefined, /* undefined [011001xxxxxxxxxxxxxxxx] */
kMipsLast
-} MipsOpCode;
+};
/* Bit flags describing the behavior of each native opcode */
-typedef enum MipsOpFeatureFlags {
+enum MipsOpFeatureFlags {
kIsBranch = 0,
kRegDef0,
kRegDef1,
@@ -472,7 +472,7 @@
kMemStore,
kPCRelFixup,
kRegUseLR,
-} MipsOpFeatureFlags;
+};
#define IS_LOAD (1 << kMemLoad)
#define IS_STORE (1 << kMemStore)
@@ -522,16 +522,16 @@
#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2)
/* Instruction assembly fieldLoc kind */
-typedef enum MipsEncodingKind {
+enum MipsEncodingKind {
kFmtUnused,
kFmtBitBlt, /* Bit string using end/start */
kFmtDfp, /* Double FP reg */
kFmtSfp, /* Single FP reg */
kFmtBlt5_2, /* Same 5-bit field to 2 locations */
-} MipsEncodingKind;
+};
/* Struct used to define the snippet positions for each MIPS opcode */
-typedef struct MipsEncodingMap {
+struct MipsEncodingMap {
u4 skeleton;
struct {
MipsEncodingKind kind;
@@ -543,12 +543,12 @@
const char *name;
const char* fmt;
int size; /* Size in bytes */
-} MipsEncodingMap;
+};
/* Keys for target-specific scheduling and other optimization hints */
-typedef enum MipsTargetOptHints {
+enum MipsTargetOptHints {
kMaxHoistDistance,
-} MipsTargetOptHints;
+};
extern MipsEncodingMap EncodingMap[kMipsLast];
diff --git a/src/compiler/codegen/x86/X86LIR.h b/src/compiler/codegen/x86/X86LIR.h
index 32bb1f8..31449e0 100644
--- a/src/compiler/codegen/x86/X86LIR.h
+++ b/src/compiler/codegen/x86/X86LIR.h
@@ -138,7 +138,7 @@
INVALID_SREG}
#define LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 1, rAX, rDX, INVALID_SREG}
-typedef enum ResourceEncodingPos {
+enum ResourceEncodingPos {
kGPReg0 = 0,
kRegSP = 4,
kRegLR = -1,
@@ -151,7 +151,7 @@
kLiteral, // 2 Literal pool (can be fully disambiguated)
kHeapRef, // 3 Somewhere on the heap (alias with any other heap)
kMustNotAlias, // 4 Guaranteed to be non-alias (eg *(r6+x))
-} ResourceEncodingPos;
+};
#define ENCODE_REG_LIST(N) ((u8) N)
#define ENCODE_REG_SP (1ULL << kRegSP)
@@ -175,7 +175,7 @@
* Annotate special-purpose core registers:
*/
-typedef enum NativeRegisterPool {
+enum NativeRegisterPool {
r0 = 0,
rAX = r0,
r1 = 1,
@@ -216,7 +216,7 @@
fr13 = 13 + FP_REG_OFFSET,
fr14 = 14 + FP_REG_OFFSET,
fr15 = 15 + FP_REG_OFFSET,
-} NativeRegisterPool;
+};
/*
* Target-independent aliases
@@ -235,7 +235,7 @@
* assembler. Their corresponding EncodingMap positions will be defined in
* Assemble.cc.
*/
-typedef enum X86OpCode {
+enum X86OpCode {
kPseudoSuspendTarget = -15,
kPseudoThrowTarget = -14,
kPseudoCaseLabel = -13,
@@ -285,25 +285,25 @@
BinaryOpCode(kOpMov),
#undef BinaryOpCode
kX86Last
-} X86OpCode;
+};
/* Instruction assembly fieldLoc kind */
-typedef enum X86EncodingKind {
+enum X86EncodingKind {
kData, // Special case for raw data
kRegImm, kMemImm, kArrayImm, // RI, MI, AI instruction kinds
kRegReg, kRegMem, kRegArray, // RR, RM, RA instruction kinds
kMemReg, kArrayReg, // MR and AR instruction kinds
kUnimplemented // Encoding used when an instruction isn't yet implemented.
-} X86EncodingKind;
+};
/* A form of instruction with an opcode byte and a secondary opcode within the modrm byte */
-typedef struct OpcodeModRMOpcode {
+struct OpcodeModRMOpcode {
uint8_t opcode; // 1 byte opcode
uint8_t modrm_opcode; // 3 bit opcode that gets encoded in the register bits of the modrm byte
-} OpcodeModRMOpcode;
+};
/* Struct used to define the EncodingMap positions for each X86 opcode */
-typedef struct X86EncodingMap {
+struct X86EncodingMap {
X86OpCode opcode; // e.g. kOpAddRI
X86EncodingKind kind; // Used to discriminate in the union below
int flags;
@@ -328,7 +328,7 @@
} skeleton;
const char *name;
const char* fmt;
-} X86EncodingMap;
+};
extern X86EncodingMap EncodingMap[kX86Last];
@@ -337,7 +337,7 @@
#define kST 0
/* Bit flags describing the behavior of each native opcode */
-typedef enum X86OpFeatureFlags {
+enum X86OpFeatureFlags {
kIsBranch = 0,
kRegDef0,
kRegDef1,
@@ -363,7 +363,7 @@
kMemStore,
kPCRelFixup,
// FIXME: add NEEDS_FIXUP to instruction attributes
-} X86OpFeatureFlags;
+};
#define IS_LOAD (1 << kMemLoad)
#define IS_STORE (1 << kMemStore)
@@ -412,9 +412,9 @@
#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2)
/* Keys for target-specific scheduling and other optimization hints */
-typedef enum X86TargetOptHints {
+enum X86TargetOptHints {
kMaxHoistDistance,
-} X86TargetOptHints;
+};
#define IS_SIMM8(v) ((-128 <= (v)) && ((v) <= 127))