ARM: Support SIMD reduction for 32-bit backend.
Support SIMD reduction (add, min, max) and SAD (for int->int only)
idioms for arm (32-bit) backend.
Test: test-art-target, test-art-host
Test: 661-checker-simd-reduc, 660-checker-simd-sad-int
Change-Id: Ic6121f5d781a9bcedc33041b6c4ecafad9b0420a
diff --git a/compiler/optimizing/loop_optimization.cc b/compiler/optimizing/loop_optimization.cc
index d87861b..645915e 100644
--- a/compiler/optimizing/loop_optimization.cc
+++ b/compiler/optimizing/loop_optimization.cc
@@ -1359,7 +1359,7 @@
*restrictions |= kNoDiv | kNoStringCharAt | kNoReduction;
return TrySetVectorLength(4);
case DataType::Type::kInt32:
- *restrictions |= kNoDiv | kNoReduction;
+ *restrictions |= kNoDiv | kNoWideSAD;
return TrySetVectorLength(2);
default:
break;
@@ -1968,7 +1968,9 @@
return false;
}
// Try same/narrower type and deal with vector restrictions.
- if (!TrySetVectorType(sub_type, &restrictions) || HasVectorRestrictions(restrictions, kNoSAD)) {
+ if (!TrySetVectorType(sub_type, &restrictions) ||
+ HasVectorRestrictions(restrictions, kNoSAD) ||
+ (reduction_type != sub_type && HasVectorRestrictions(restrictions, kNoWideSAD))) {
return false;
}
// Accept SAD idiom for vectorizable operands. Vectorized code uses the shorthand