Revert "Revert "Enable Load Store Elimination for ARM and ARM64""
This patch refactors the implementation of the LoadStoreElimination
optimisation pass. Please note that this pass was disabled and not
functional for any of the backends.
The current implementation tracks aliases and handles DalvikRegs as well
as Heap memory regions. It has been tested and it is known to optimise
out the following:
* Load - Load
* Store - Load
* Store - Store
* Load Literals
Change-Id: I3aadb12a787164146a95bc314e85fa73ad91e12b
diff --git a/compiler/dex/quick/mir_to_lir.h b/compiler/dex/quick/mir_to_lir.h
index b832223..d03b859 100644
--- a/compiler/dex/quick/mir_to_lir.h
+++ b/compiler/dex/quick/mir_to_lir.h
@@ -51,6 +51,7 @@
#define IS_BINARY_OP (1ULL << kIsBinaryOp)
#define IS_BRANCH (1ULL << kIsBranch)
#define IS_IT (1ULL << kIsIT)
+#define IS_MOVE (1ULL << kIsMoveOp)
#define IS_LOAD (1ULL << kMemLoad)
#define IS_QUAD_OP (1ULL << kIsQuadOp)
#define IS_QUIN_OP (1ULL << kIsQuinOp)
@@ -58,6 +59,7 @@
#define IS_STORE (1ULL << kMemStore)
#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp)
#define IS_UNARY_OP (1ULL << kIsUnaryOp)
+#define IS_VOLATILE (1ULL << kMemVolatile)
#define NEEDS_FIXUP (1ULL << kPCRelFixup)
#define NO_OPERAND (1ULL << kNoOperand)
#define REG_DEF0 (1ULL << kRegDef0)
@@ -94,6 +96,20 @@
#define REG_USE_HI (1ULL << kUseHi)
#define REG_DEF_LO (1ULL << kDefLo)
#define REG_DEF_HI (1ULL << kDefHi)
+#define SCALED_OFFSET_X0 (1ULL << kMemScaledx0)
+#define SCALED_OFFSET_X2 (1ULL << kMemScaledx2)
+#define SCALED_OFFSET_X4 (1ULL << kMemScaledx4)
+
+// Special load/stores
+#define IS_LOADX (IS_LOAD | IS_VOLATILE)
+#define IS_LOAD_OFF (IS_LOAD | SCALED_OFFSET_X0)
+#define IS_LOAD_OFF2 (IS_LOAD | SCALED_OFFSET_X2)
+#define IS_LOAD_OFF4 (IS_LOAD | SCALED_OFFSET_X4)
+
+#define IS_STOREX (IS_STORE | IS_VOLATILE)
+#define IS_STORE_OFF (IS_STORE | SCALED_OFFSET_X0)
+#define IS_STORE_OFF2 (IS_STORE | SCALED_OFFSET_X2)
+#define IS_STORE_OFF4 (IS_STORE | SCALED_OFFSET_X4)
// Common combo register usage patterns.
#define REG_DEF01 (REG_DEF0 | REG_DEF1)
@@ -552,6 +568,12 @@
virtual ~Mir2Lir() {}
+ /**
+ * @brief Decodes the LIR offset.
+ * @return Returns the scaled offset of LIR.
+ */
+ virtual size_t GetInstructionOffset(LIR* lir);
+
int32_t s4FromSwitchData(const void* switch_data) {
return *reinterpret_cast<const int32_t*>(switch_data);
}
@@ -641,7 +663,10 @@
void SetMemRefType(LIR* lir, bool is_load, int mem_type);
void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit);
void SetupRegMask(ResourceMask* mask, int reg);
+ void ClearRegMask(ResourceMask* mask, int reg);
void DumpLIRInsn(LIR* arg, unsigned char* base_addr);
+ void EliminateLoad(LIR* lir, int reg_id);
+ void DumpDependentInsnPair(LIR* check_lir, LIR* this_lir, const char* type);
void DumpPromotionMap();
void CodegenDump();
LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0,