commit 611d3395e9efc0ab8dbfa4a197fa022fbd8c7204
author Scott Wakeling <scott.wakeling@linaro.org> Fri Jul 10 11:42:06 2015 +0100
committer Scott Wakeling <scott.wakeling@linaro.org> Tue Aug 04 09:02:56 2015 +0100
tree 9a0a3b6750caae13b963b244719e03b8cfb49c44
parent 0c9c5bbdd6976c21602b92d9b455e6fe5d769fb0

ARM/ARM64: Implement numberOfLeadingZeros intrinsic.

Change-Id: I4042fb7a0b75140475dcfca23e8f79d310f5333b

disassembler/disassembler_arm.cc

diff --git a/disassembler/disassembler_arm.cc b/disassembler/disassembler_arm.cc
index 31e653b..d1d3481 100644
--- a/disassembler/disassembler_arm.cc
+++ b/disassembler/disassembler_arm.cc
@@ -1455,6 +1455,20 @@
           }  // else unknown instruction
           break;
         }
+        case 0x2B: {  // 0101011
+          //  CLZ - 111 11 0101011 mmmm 1111 dddd 1000 mmmm
+          if ((instr & 0xf0f0) == 0xf080) {
+            opcode << "clz";
+            ArmRegister Rm(instr, 0);
+            ArmRegister Rd(instr, 8);
+            args << Rd << ", " << Rm;
+            ArmRegister Rm2(instr, 16);
+            if (Rm.r != Rm2.r || Rm.r == 13 || Rm.r == 15 || Rd.r == 13 || Rd.r == 15) {
+              args << " (UNPREDICTABLE)";
+            }
+          }
+          break;
+        }
       default:      // more formats
         if ((op2 >> 4) == 2) {      // 010xxxx
           // data processing (register)