commit 5a4fa82ab42af6e728a60e3261963aa243c3e2cd
author Andreas Gampe <agampe@google.com> Mon Mar 31 16:50:12 2014 -0700
committer Andreas Gampe <agampe@google.com> Wed Apr 30 19:25:51 2014 -0700
tree 69da9eb204c294be63f30d49cf0233e1dc9b6e93
parent 0a3b13fc401bcf21225e30654012fe98806b0873

x86_64 Assembler Test Infrastructure, fix x86_64 assembler

Some infrastructure to do real assembler testing. Need to extend to
other assemblers, and a lot more tests.

Fix some of the cases of the x86_64 assembler.

Change-Id: I15b5f3a094af469130db68a95a66602cf30d8fc4

compiler/utils/x86_64/assembler_x86_64.h

diff --git a/compiler/utils/x86_64/assembler_x86_64.h b/compiler/utils/x86_64/assembler_x86_64.h
index 4738dcb..87fb359 100644
--- a/compiler/utils/x86_64/assembler_x86_64.h
+++ b/compiler/utils/x86_64/assembler_x86_64.h
@@ -31,16 +31,21 @@
 
 class Immediate {
  public:
-  explicit Immediate(int32_t value) : value_(value) {}
+  explicit Immediate(int64_t value) : value_(value) {}
 
-  int32_t value() const { return value_; }
+  int64_t value() const { return value_; }
 
   bool is_int8() const { return IsInt(8, value_); }
   bool is_uint8() const { return IsUint(8, value_); }
   bool is_uint16() const { return IsUint(16, value_); }
+  bool is_int32() const {
+    // This does not work on 32b machines: return IsInt(32, value_);
+    int64_t limit = static_cast<int64_t>(1) << 31;
+    return (-limit <= value_) && (value_ < limit);
+  }
 
  private:
-  const int32_t value_;
+  const int64_t value_;
 
   DISALLOW_COPY_AND_ASSIGN(Immediate);
 };
@@ -368,10 +373,11 @@
   void cmpl(CpuRegister reg, const Immediate& imm);
   void cmpl(CpuRegister reg0, CpuRegister reg1);
   void cmpl(CpuRegister reg, const Address& address);
-
   void cmpl(const Address& address, CpuRegister reg);
   void cmpl(const Address& address, const Immediate& imm);
 
+  void cmpq(CpuRegister reg0, CpuRegister reg1);
+
   void testl(CpuRegister reg1, CpuRegister reg2);
   void testl(CpuRegister reg, const Immediate& imm);
 
@@ -382,19 +388,24 @@
   void orl(CpuRegister dst, CpuRegister src);
 
   void xorl(CpuRegister dst, CpuRegister src);
+  void xorq(CpuRegister dst, const Immediate& imm);
 
   void addl(CpuRegister dst, CpuRegister src);
-  void addq(CpuRegister reg, const Immediate& imm);
   void addl(CpuRegister reg, const Immediate& imm);
   void addl(CpuRegister reg, const Address& address);
-
   void addl(const Address& address, CpuRegister reg);
   void addl(const Address& address, const Immediate& imm);
 
+  void addq(CpuRegister reg, const Immediate& imm);
+  void addq(CpuRegister dst, CpuRegister src);
+
   void subl(CpuRegister dst, CpuRegister src);
   void subl(CpuRegister reg, const Immediate& imm);
   void subl(CpuRegister reg, const Address& address);
 
+  void subq(CpuRegister reg, const Immediate& imm);
+  void subq(CpuRegister dst, CpuRegister src);
+
   void cdq();
 
   void idivl(CpuRegister reg);
@@ -442,6 +453,8 @@
 
   X86_64Assembler* gs();
 
+  void setcc(Condition condition, CpuRegister dst);
+
   //
   // Macros for High-level operations.
   //
@@ -586,6 +599,7 @@
  private:
   void EmitUint8(uint8_t value);
   void EmitInt32(int32_t value);
+  void EmitInt64(int64_t value);
   void EmitRegisterOperand(uint8_t rm, uint8_t reg);
   void EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg);
   void EmitFixup(AssemblerFixup* fixup);
@@ -634,6 +648,10 @@
   buffer_.Emit<int32_t>(value);
 }
 
+inline void X86_64Assembler::EmitInt64(int64_t value) {
+  buffer_.Emit<int64_t>(value);
+}
+
 inline void X86_64Assembler::EmitRegisterOperand(uint8_t rm, uint8_t reg) {
   CHECK_GE(rm, 0);
   CHECK_LT(rm, 8);