commit 584771b5a85843700289ffcd36a46f3b187ca349
author Andreas Gampe <agampe@google.com> Thu Oct 18 13:22:23 2018 -0700
committer Andreas Gampe <agampe@google.com> Fri Oct 19 12:14:10 2018 -0700
tree a88996e445a1a2aee66e15ee58b977891ddf9618
parent 6bc39b1e080d574a0ed0c4dabe4d0895dd40456c

ART: Fix tidy bugprone-macro-parentheses

Add parens where necessary, add NOLINT for the cases where it's wrong.

Bug: 32619234
Test: WITH_TIDY=1 mmma art
Change-Id: If56ce51c078e9adf26b9469a01c95a857aac66a4

tools/veridex/flow_analysis.cc

diff --git a/tools/veridex/flow_analysis.cc b/tools/veridex/flow_analysis.cc
index e925e1d..1fca7e1 100644
--- a/tools/veridex/flow_analysis.cc
+++ b/tools/veridex/flow_analysis.cc
@@ -162,7 +162,7 @@
     case Instruction::IF_##cond##Z: { \
       RegisterValue val = GetRegister(instruction.VRegA()); \
       if (val.IsConstant()) { \
-        if (val.GetConstant() op 0) { \
+        if (val.GetConstant() op 0) {  /* NOLINT */ \
           return Instruction::kBranch; \
         } else { \
           return Instruction::kContinue; \