tree 5fcc2567a1a4e6ae73dead2f70c69bc03b0a64bb
parent ac27ac01490f53f9e2413dc9b66fbb2880904c96
author Artem Serov <artem.serov@linaro.org> 1588017748 +0100
committer Ulyana Trafimovich <skvadrik@google.com> 1612524878 +0000

ARM64: Support SVE VL other than 128-bit.

Arm SVE register size is not fixed and can be a
multiple of 128 bits. To support that the patch
removes explicit assumptions on the SIMD register
size to be 128 bit from the vectorizer and code
generators and enables configurable SVE vector
length autovectorization, e.g. extends SIMD register
save/restore routines.

Test: art SIMD tests on VIXL simulator.
Test: art tests on FVP (steps in test/README.arm_fvp.md)
      with FVP arg:
      -C SVE.ScalableVectorExtension.veclen=[2,4]
      (SVE vector [128,256] bits wide)

Change-Id: Icb46e7eb17f21d3bd38b16dd50f735c29b316427