ART: Refactor for bugprone-argument-comment
Handles compiler.
Bug: 116054210
Test: WITH_TIDY=1 mmma art
Change-Id: I5cdfe73c31ac39144838a2736146b71de037425e
diff --git a/compiler/utils/mips64/assembler_mips64.cc b/compiler/utils/mips64/assembler_mips64.cc
index 29d2bed..70313ca 100644
--- a/compiler/utils/mips64/assembler_mips64.cc
+++ b/compiler/utils/mips64/assembler_mips64.cc
@@ -2455,7 +2455,7 @@
condition_(kUncond) {
InitializeType(
(is_call ? (is_bare ? kBareCall : kCall) : (is_bare ? kBareCondBranch : kCondBranch)),
- /* is_r6 */ true);
+ /* is_r6= */ true);
}
Mips64Assembler::Branch::Branch(bool is_r6,
@@ -2516,7 +2516,7 @@
rhs_reg_(ZERO),
condition_(kUncond) {
CHECK_NE(dest_reg, ZERO);
- InitializeType(label_or_literal_type, /* is_r6 */ true);
+ InitializeType(label_or_literal_type, /* is_r6= */ true);
}
Mips64Assembler::BranchCondition Mips64Assembler::Branch::OppositeCondition(
@@ -2896,7 +2896,7 @@
void Mips64Assembler::Buncond(Mips64Label* label, bool is_bare) {
uint32_t target = label->IsBound() ? GetLabelLocation(label) : Branch::kUnresolved;
- branches_.emplace_back(buffer_.Size(), target, /* is_call */ false, is_bare);
+ branches_.emplace_back(buffer_.Size(), target, /* is_call= */ false, is_bare);
FinalizeLabeledBranch(label);
}
@@ -2917,7 +2917,7 @@
void Mips64Assembler::Call(Mips64Label* label, bool is_bare) {
uint32_t target = label->IsBound() ? GetLabelLocation(label) : Branch::kUnresolved;
- branches_.emplace_back(buffer_.Size(), target, /* is_call */ true, is_bare);
+ branches_.emplace_back(buffer_.Size(), target, /* is_call= */ true, is_bare);
FinalizeLabeledBranch(label);
}
@@ -3278,99 +3278,99 @@
}
void Mips64Assembler::Bltc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) {
- Bcond(label, /* is_r6 */ true, is_bare, kCondLT, rs, rt);
+ Bcond(label, /* is_r6= */ true, is_bare, kCondLT, rs, rt);
}
void Mips64Assembler::Bltzc(GpuRegister rt, Mips64Label* label, bool is_bare) {
- Bcond(label, /* is_r6 */ true, is_bare, kCondLTZ, rt);
+ Bcond(label, /* is_r6= */ true, is_bare, kCondLTZ, rt);
}
void Mips64Assembler::Bgtzc(GpuRegister rt, Mips64Label* label, bool is_bare) {
- Bcond(label, /* is_r6 */ true, is_bare, kCondGTZ, rt);
+ Bcond(label, /* is_r6= */ true, is_bare, kCondGTZ, rt);
}
void Mips64Assembler::Bgec(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) {
- Bcond(label, /* is_r6 */ true, is_bare, kCondGE, rs, rt);
+ Bcond(label, /* is_r6= */ true, is_bare, kCondGE, rs, rt);
}
void Mips64Assembler::Bgezc(GpuRegister rt, Mips64Label* label, bool is_bare) {
- Bcond(label, /* is_r6 */ true, is_bare, kCondGEZ, rt);
+ Bcond(label, /* is_r6= */ true, is_bare, kCondGEZ, rt);
}
void Mips64Assembler::Blezc(GpuRegister rt, Mips64Label* label, bool is_bare) {
- Bcond(label, /* is_r6 */ true, is_bare, kCondLEZ, rt);
+ Bcond(label, /* is_r6= */ true, is_bare, kCondLEZ, rt);
}
void Mips64Assembler::Bltuc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) {
- Bcond(label, /* is_r6 */ true, is_bare, kCondLTU, rs, rt);
+ Bcond(label, /* is_r6= */ true, is_bare, kCondLTU, rs, rt);
}
void Mips64Assembler::Bgeuc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) {
- Bcond(label, /* is_r6 */ true, is_bare, kCondGEU, rs, rt);
+ Bcond(label, /* is_r6= */ true, is_bare, kCondGEU, rs, rt);
}
void Mips64Assembler::Beqc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) {
- Bcond(label, /* is_r6 */ true, is_bare, kCondEQ, rs, rt);
+ Bcond(label, /* is_r6= */ true, is_bare, kCondEQ, rs, rt);
}
void Mips64Assembler::Bnec(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) {
- Bcond(label, /* is_r6 */ true, is_bare, kCondNE, rs, rt);
+ Bcond(label, /* is_r6= */ true, is_bare, kCondNE, rs, rt);
}
void Mips64Assembler::Beqzc(GpuRegister rs, Mips64Label* label, bool is_bare) {
- Bcond(label, /* is_r6 */ true, is_bare, kCondEQZ, rs);
+ Bcond(label, /* is_r6= */ true, is_bare, kCondEQZ, rs);
}
void Mips64Assembler::Bnezc(GpuRegister rs, Mips64Label* label, bool is_bare) {
- Bcond(label, /* is_r6 */ true, is_bare, kCondNEZ, rs);
+ Bcond(label, /* is_r6= */ true, is_bare, kCondNEZ, rs);
}
void Mips64Assembler::Bc1eqz(FpuRegister ft, Mips64Label* label, bool is_bare) {
- Bcond(label, /* is_r6 */ true, is_bare, kCondF, static_cast<GpuRegister>(ft), ZERO);
+ Bcond(label, /* is_r6= */ true, is_bare, kCondF, static_cast<GpuRegister>(ft), ZERO);
}
void Mips64Assembler::Bc1nez(FpuRegister ft, Mips64Label* label, bool is_bare) {
- Bcond(label, /* is_r6 */ true, is_bare, kCondT, static_cast<GpuRegister>(ft), ZERO);
+ Bcond(label, /* is_r6= */ true, is_bare, kCondT, static_cast<GpuRegister>(ft), ZERO);
}
void Mips64Assembler::Bltz(GpuRegister rt, Mips64Label* label, bool is_bare) {
CHECK(is_bare);
- Bcond(label, /* is_r6 */ false, is_bare, kCondLTZ, rt);
+ Bcond(label, /* is_r6= */ false, is_bare, kCondLTZ, rt);
}
void Mips64Assembler::Bgtz(GpuRegister rt, Mips64Label* label, bool is_bare) {
CHECK(is_bare);
- Bcond(label, /* is_r6 */ false, is_bare, kCondGTZ, rt);
+ Bcond(label, /* is_r6= */ false, is_bare, kCondGTZ, rt);
}
void Mips64Assembler::Bgez(GpuRegister rt, Mips64Label* label, bool is_bare) {
CHECK(is_bare);
- Bcond(label, /* is_r6 */ false, is_bare, kCondGEZ, rt);
+ Bcond(label, /* is_r6= */ false, is_bare, kCondGEZ, rt);
}
void Mips64Assembler::Blez(GpuRegister rt, Mips64Label* label, bool is_bare) {
CHECK(is_bare);
- Bcond(label, /* is_r6 */ false, is_bare, kCondLEZ, rt);
+ Bcond(label, /* is_r6= */ false, is_bare, kCondLEZ, rt);
}
void Mips64Assembler::Beq(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) {
CHECK(is_bare);
- Bcond(label, /* is_r6 */ false, is_bare, kCondEQ, rs, rt);
+ Bcond(label, /* is_r6= */ false, is_bare, kCondEQ, rs, rt);
}
void Mips64Assembler::Bne(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) {
CHECK(is_bare);
- Bcond(label, /* is_r6 */ false, is_bare, kCondNE, rs, rt);
+ Bcond(label, /* is_r6= */ false, is_bare, kCondNE, rs, rt);
}
void Mips64Assembler::Beqz(GpuRegister rs, Mips64Label* label, bool is_bare) {
CHECK(is_bare);
- Bcond(label, /* is_r6 */ false, is_bare, kCondEQZ, rs);
+ Bcond(label, /* is_r6= */ false, is_bare, kCondEQZ, rs);
}
void Mips64Assembler::Bnez(GpuRegister rs, Mips64Label* label, bool is_bare) {
CHECK(is_bare);
- Bcond(label, /* is_r6 */ false, is_bare, kCondNEZ, rs);
+ Bcond(label, /* is_r6= */ false, is_bare, kCondNEZ, rs);
}
void Mips64Assembler::AdjustBaseAndOffset(GpuRegister& base,
diff --git a/compiler/utils/mips64/assembler_mips64.h b/compiler/utils/mips64/assembler_mips64.h
index ce447db..2f991e9 100644
--- a/compiler/utils/mips64/assembler_mips64.h
+++ b/compiler/utils/mips64/assembler_mips64.h
@@ -1058,7 +1058,7 @@
// We permit `base` and `temp` to coincide (however, we check that neither is AT),
// in which case the `base` register may be overwritten in the process.
CHECK_NE(temp, AT); // Must not use AT as temp, so as not to overwrite the adjusted base.
- AdjustBaseAndOffset(base, offset, /* is_doubleword */ (type == kStoreDoubleword));
+ AdjustBaseAndOffset(base, offset, /* is_doubleword= */ (type == kStoreDoubleword));
GpuRegister reg;
// If the adjustment left `base` unchanged and equal to `temp`, we can't use `temp`
// to load and hold the value but we can use AT instead as AT hasn't been used yet.
@@ -1127,7 +1127,7 @@
GpuRegister base,
int32_t offset,
ImplicitNullChecker null_checker = NoImplicitNullChecker()) {
- AdjustBaseAndOffset(base, offset, /* is_doubleword */ (type == kLoadDoubleword));
+ AdjustBaseAndOffset(base, offset, /* is_doubleword= */ (type == kLoadDoubleword));
switch (type) {
case kLoadSignedByte:
@@ -1178,7 +1178,7 @@
ImplicitNullChecker null_checker = NoImplicitNullChecker()) {
int element_size_shift = -1;
if (type != kLoadQuadword) {
- AdjustBaseAndOffset(base, offset, /* is_doubleword */ (type == kLoadDoubleword));
+ AdjustBaseAndOffset(base, offset, /* is_doubleword= */ (type == kLoadDoubleword));
} else {
AdjustBaseOffsetAndElementSizeShift(base, offset, element_size_shift);
}
@@ -1226,7 +1226,7 @@
// Must not use AT as `reg`, so as not to overwrite the value being stored
// with the adjusted `base`.
CHECK_NE(reg, AT);
- AdjustBaseAndOffset(base, offset, /* is_doubleword */ (type == kStoreDoubleword));
+ AdjustBaseAndOffset(base, offset, /* is_doubleword= */ (type == kStoreDoubleword));
switch (type) {
case kStoreByte:
@@ -1267,7 +1267,7 @@
ImplicitNullChecker null_checker = NoImplicitNullChecker()) {
int element_size_shift = -1;
if (type != kStoreQuadword) {
- AdjustBaseAndOffset(base, offset, /* is_doubleword */ (type == kStoreDoubleword));
+ AdjustBaseAndOffset(base, offset, /* is_doubleword= */ (type == kStoreDoubleword));
} else {
AdjustBaseOffsetAndElementSizeShift(base, offset, element_size_shift);
}
diff --git a/compiler/utils/mips64/assembler_mips64_test.cc b/compiler/utils/mips64/assembler_mips64_test.cc
index 66711c3..499e8f4 100644
--- a/compiler/utils/mips64/assembler_mips64_test.cc
+++ b/compiler/utils/mips64/assembler_mips64_test.cc
@@ -852,99 +852,99 @@
}
TEST_F(AssemblerMIPS64Test, BareBc) {
- BranchHelper(&mips64::Mips64Assembler::Bc, "Bc", /* is_bare */ true);
+ BranchHelper(&mips64::Mips64Assembler::Bc, "Bc", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBalc) {
- BranchHelper(&mips64::Mips64Assembler::Balc, "Balc", /* is_bare */ true);
+ BranchHelper(&mips64::Mips64Assembler::Balc, "Balc", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBeqzc) {
- BranchCondOneRegHelper(&mips64::Mips64Assembler::Beqzc, "Beqzc", /* is_bare */ true);
+ BranchCondOneRegHelper(&mips64::Mips64Assembler::Beqzc, "Beqzc", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBnezc) {
- BranchCondOneRegHelper(&mips64::Mips64Assembler::Bnezc, "Bnezc", /* is_bare */ true);
+ BranchCondOneRegHelper(&mips64::Mips64Assembler::Bnezc, "Bnezc", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBltzc) {
- BranchCondOneRegHelper(&mips64::Mips64Assembler::Bltzc, "Bltzc", /* is_bare */ true);
+ BranchCondOneRegHelper(&mips64::Mips64Assembler::Bltzc, "Bltzc", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBgezc) {
- BranchCondOneRegHelper(&mips64::Mips64Assembler::Bgezc, "Bgezc", /* is_bare */ true);
+ BranchCondOneRegHelper(&mips64::Mips64Assembler::Bgezc, "Bgezc", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBlezc) {
- BranchCondOneRegHelper(&mips64::Mips64Assembler::Blezc, "Blezc", /* is_bare */ true);
+ BranchCondOneRegHelper(&mips64::Mips64Assembler::Blezc, "Blezc", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBgtzc) {
- BranchCondOneRegHelper(&mips64::Mips64Assembler::Bgtzc, "Bgtzc", /* is_bare */ true);
+ BranchCondOneRegHelper(&mips64::Mips64Assembler::Bgtzc, "Bgtzc", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBeqc) {
- BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Beqc, "Beqc", /* is_bare */ true);
+ BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Beqc, "Beqc", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBnec) {
- BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bnec, "Bnec", /* is_bare */ true);
+ BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bnec, "Bnec", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBltc) {
- BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bltc, "Bltc", /* is_bare */ true);
+ BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bltc, "Bltc", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBgec) {
- BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bgec, "Bgec", /* is_bare */ true);
+ BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bgec, "Bgec", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBltuc) {
- BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bltuc, "Bltuc", /* is_bare */ true);
+ BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bltuc, "Bltuc", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBgeuc) {
- BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bgeuc, "Bgeuc", /* is_bare */ true);
+ BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bgeuc, "Bgeuc", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBc1eqz) {
- BranchFpuCondHelper(&mips64::Mips64Assembler::Bc1eqz, "Bc1eqz", /* is_bare */ true);
+ BranchFpuCondHelper(&mips64::Mips64Assembler::Bc1eqz, "Bc1eqz", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBc1nez) {
- BranchFpuCondHelper(&mips64::Mips64Assembler::Bc1nez, "Bc1nez", /* is_bare */ true);
+ BranchFpuCondHelper(&mips64::Mips64Assembler::Bc1nez, "Bc1nez", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBeqz) {
- BranchCondOneRegHelper(&mips64::Mips64Assembler::Beqz, "Beqz", /* is_bare */ true);
+ BranchCondOneRegHelper(&mips64::Mips64Assembler::Beqz, "Beqz", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBnez) {
- BranchCondOneRegHelper(&mips64::Mips64Assembler::Bnez, "Bnez", /* is_bare */ true);
+ BranchCondOneRegHelper(&mips64::Mips64Assembler::Bnez, "Bnez", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBltz) {
- BranchCondOneRegHelper(&mips64::Mips64Assembler::Bltz, "Bltz", /* is_bare */ true);
+ BranchCondOneRegHelper(&mips64::Mips64Assembler::Bltz, "Bltz", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBgez) {
- BranchCondOneRegHelper(&mips64::Mips64Assembler::Bgez, "Bgez", /* is_bare */ true);
+ BranchCondOneRegHelper(&mips64::Mips64Assembler::Bgez, "Bgez", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBlez) {
- BranchCondOneRegHelper(&mips64::Mips64Assembler::Blez, "Blez", /* is_bare */ true);
+ BranchCondOneRegHelper(&mips64::Mips64Assembler::Blez, "Blez", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBgtz) {
- BranchCondOneRegHelper(&mips64::Mips64Assembler::Bgtz, "Bgtz", /* is_bare */ true);
+ BranchCondOneRegHelper(&mips64::Mips64Assembler::Bgtz, "Bgtz", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBeq) {
- BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Beq, "Beq", /* is_bare */ true);
+ BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Beq, "Beq", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, BareBne) {
- BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bne, "Bne", /* is_bare */ true);
+ BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bne, "Bne", /* is_bare= */ true);
}
TEST_F(AssemblerMIPS64Test, LongBeqc) {
@@ -1252,7 +1252,7 @@
std::vector<mips64::GpuRegister*> reg1_registers = GetRegisters();
std::vector<mips64::GpuRegister*> reg2_registers = GetRegisters();
reg2_registers.erase(reg2_registers.begin()); // reg2 can't be ZERO, remove it.
- std::vector<int64_t> imms = CreateImmediateValuesBits(/* imm_bits */ 16, /* as_uint */ true);
+ std::vector<int64_t> imms = CreateImmediateValuesBits(/* imm_bits= */ 16, /* as_uint= */ true);
WarnOnCombinations(reg1_registers.size() * reg2_registers.size() * imms.size());
std::ostringstream expected;
for (mips64::GpuRegister* reg1 : reg1_registers) {