commit 3da67a558f1fd3d8a157d8044d521753f3f99ac8
author Dave Allison <dallison@google.com> Wed Apr 02 17:03:45 2014 -0700
committer Dave Allison <dallison@google.com> Thu Apr 03 12:27:32 2014 -0700
tree 1db98475511e4c5ec2af8cabcfbdb985a963dded
parent 0537c5ea92a4fb60a04024cc2b7247f08a3d9096

Add OpEndIT() for marking the end of OpIT blocks

In ARM we need to prevent code motion to the inside of an
IT block.  This was done using a GenBarrier() to mark the end, but
it wasn't obvious that this is what was happening.  This CL adds
an explicit OpEndIT() that takes the LIR of the OpIT for future
checks.

Bug: 13751744
Change-Id: If41d2adea1f43f11ebb3b72906bd308252ce3d01

compiler/dex/quick/gen_common.cc

diff --git a/compiler/dex/quick/gen_common.cc b/compiler/dex/quick/gen_common.cc
index c5c42e8..bfa22da 100644
--- a/compiler/dex/quick/gen_common.cc
+++ b/compiler/dex/quick/gen_common.cc
@@ -1082,9 +1082,9 @@
   LIR* ne_branchover = NULL;
   if (cu_->instruction_set == kThumb2) {
     OpRegReg(kOpCmp, check_class, object_class);  // Same?
-    OpIT(kCondEq, "");   // if-convert the test
+    LIR* it = OpIT(kCondEq, "");   // if-convert the test
     LoadConstant(result_reg, 1);     // .eq case - load true
-    GenBarrier();
+    OpEndIT(it);
   } else {
     ne_branchover = OpCmpBranch(kCondNe, check_class, object_class, NULL);
     LoadConstant(result_reg, 1);     // eq case - load true
@@ -1166,10 +1166,10 @@
     // rl_result == ref == null == 0.
     if (cu_->instruction_set == kThumb2) {
       OpRegReg(kOpCmp, TargetReg(kArg1), TargetReg(kArg2));  // Same?
-      OpIT(kCondEq, "E");   // if-convert the test
+      LIR* it = OpIT(kCondEq, "E");   // if-convert the test
       LoadConstant(rl_result.reg, 1);     // .eq case - load true
       LoadConstant(rl_result.reg, 0);     // .ne case - load false
-      GenBarrier();
+      OpEndIT(it);
     } else {
       LoadConstant(rl_result.reg, 0);     // ne case - load false
       branchover = OpCmpBranch(kCondNe, TargetReg(kArg1), TargetReg(kArg2), NULL);
@@ -1178,15 +1178,18 @@
   } else {
     if (cu_->instruction_set == kThumb2) {
       RegStorage r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial));
+      LIR* it = nullptr;
       if (!type_known_abstract) {
       /* Uses conditional nullification */
         OpRegReg(kOpCmp, TargetReg(kArg1), TargetReg(kArg2));  // Same?
-        OpIT(kCondEq, "EE");   // if-convert the test
+        it = OpIT(kCondEq, "EE");   // if-convert the test
         LoadConstant(TargetReg(kArg0), 1);     // .eq case - load true
       }
       OpRegCopy(TargetReg(kArg0), TargetReg(kArg2));    // .ne case - arg0 <= class
       OpReg(kOpBlx, r_tgt);    // .ne case: helper(class, ref->class)
-      GenBarrier();
+      if (it != nullptr) {
+        OpEndIT(it);
+      }
       FreeTemp(r_tgt);
     } else {
       if (!type_known_abstract) {