ART: Transform Sub+Sub into Sub+Add to merge Shl
In the instruction sequence like the following:
t1 = Shl(a, n)
t2 = Sub(t1, *)
r = Sub(*, t2)
Shl cannot be merged with Sub. However it can be done when the first Sub
operands are reordered and the second Sub is replaced with Add:
t1 = Shl(a, n)
t2 = Sub(*, t1)
r = Add(*, t2)
This CL implements this transformation in the ARM/ARM64 instruction simplifiers.
Test: 411-checker-instruct-simplifier-hrem
Test: test.py --host --optimizing --jit --gtest --interpreter
Test: test.py --target --optimizing --jit --interpreter
Test: run-gtests.sh
Change-Id: I24fde29d307f3ad53a8df8bbafe945b4f733ce6c
diff --git a/compiler/optimizing/instruction_simplifier_shared.h b/compiler/optimizing/instruction_simplifier_shared.h
index 758fc76..876ed21 100644
--- a/compiler/optimizing/instruction_simplifier_shared.h
+++ b/compiler/optimizing/instruction_simplifier_shared.h
@@ -47,6 +47,15 @@
return res;
}
+// Check the specified sub is the last operation of the sequence:
+// t1 = Shl
+// t2 = Sub(t1, *)
+// t3 = Sub(*, t2)
+inline bool IsSubRightSubLeftShl(HSub *sub) {
+ HInstruction* right = sub->GetRight();
+ return right->IsSub() && right->AsSub()->GetLeft()->IsShl();;
+}
+
} // namespace helpers
bool TryCombineMultiplyAccumulate(HMul* mul, InstructionSet isa);
@@ -61,6 +70,12 @@
bool TryExtractVecArrayAccessAddress(HVecMemoryOperation* access, HInstruction* index);
+// Try to replace
+// Sub(c, Sub(a, b))
+// with
+// Add(c, Sub(b, a))
+bool TryReplaceSubSubWithSubAdd(HSub* last_sub);
+
} // namespace art
#endif // ART_COMPILER_OPTIMIZING_INSTRUCTION_SIMPLIFIER_SHARED_H_