ART: Make InstructionSet an enum class and add kLast.
Adding InstructionSet::kLast shall make it easier to encode
the InstructionSet in fewer bits using BitField<>. However,
introducing `kLast` into the `art` namespace is not a good
idea, so we change the InstructionSet to an enum class.
This also uncovered a case of InstructionSet::kNone being
erroneously used instead of vixl32::Condition::None(), so
it's good to remove `kNone` from the `art` namespace.
Test: m test-art-host-gtest
Test: testrunner.py --host --optimizing
Change-Id: I6fa6168dfba4ed6da86d021a69c80224f09997a6
diff --git a/compiler/debug/elf_debug_loc_writer.h b/compiler/debug/elf_debug_loc_writer.h
index bf47e8f..bb856b2 100644
--- a/compiler/debug/elf_debug_loc_writer.h
+++ b/compiler/debug/elf_debug_loc_writer.h
@@ -33,20 +33,20 @@
static Reg GetDwarfCoreReg(InstructionSet isa, int machine_reg) {
switch (isa) {
- case kArm:
- case kThumb2:
+ case InstructionSet::kArm:
+ case InstructionSet::kThumb2:
return Reg::ArmCore(machine_reg);
- case kArm64:
+ case InstructionSet::kArm64:
return Reg::Arm64Core(machine_reg);
- case kX86:
+ case InstructionSet::kX86:
return Reg::X86Core(machine_reg);
- case kX86_64:
+ case InstructionSet::kX86_64:
return Reg::X86_64Core(machine_reg);
- case kMips:
+ case InstructionSet::kMips:
return Reg::MipsCore(machine_reg);
- case kMips64:
+ case InstructionSet::kMips64:
return Reg::Mips64Core(machine_reg);
- case kNone:
+ case InstructionSet::kNone:
LOG(FATAL) << "No instruction set";
}
UNREACHABLE();
@@ -54,20 +54,20 @@
static Reg GetDwarfFpReg(InstructionSet isa, int machine_reg) {
switch (isa) {
- case kArm:
- case kThumb2:
+ case InstructionSet::kArm:
+ case InstructionSet::kThumb2:
return Reg::ArmFp(machine_reg);
- case kArm64:
+ case InstructionSet::kArm64:
return Reg::Arm64Fp(machine_reg);
- case kX86:
+ case InstructionSet::kX86:
return Reg::X86Fp(machine_reg);
- case kX86_64:
+ case InstructionSet::kX86_64:
return Reg::X86_64Fp(machine_reg);
- case kMips:
+ case InstructionSet::kMips:
return Reg::MipsFp(machine_reg);
- case kMips64:
+ case InstructionSet::kMips64:
return Reg::Mips64Fp(machine_reg);
- case kNone:
+ case InstructionSet::kNone:
LOG(FATAL) << "No instruction set";
}
UNREACHABLE();
@@ -230,7 +230,7 @@
break; // the high word is correctly implied by the low word.
}
} else if (kind == Kind::kInFpuRegister) {
- if ((isa == kArm || isa == kThumb2) &&
+ if ((isa == InstructionSet::kArm || isa == InstructionSet::kThumb2) &&
piece == 0 && reg_hi.GetKind() == Kind::kInFpuRegister &&
reg_hi.GetValue() == value + 1 && value % 2 == 0) {
// Translate S register pair to D register (e.g. S4+S5 to D2).