Use shorter opcodes on x86 for opCmpImmBranch.
Gets instruction expansion from ~5.1 to ~4.9.
Change-Id: I14719df1f256589035635edcc20e25ebd396657c
diff --git a/src/compiler/codegen/x86/Assemble.cc b/src/compiler/codegen/x86/Assemble.cc
index 2da370d..2522283 100644
--- a/src/compiler/codegen/x86/Assemble.cc
+++ b/src/compiler/codegen/x86/Assemble.cc
@@ -220,6 +220,7 @@
{ kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" },
{ kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" },
{ kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },
+ { kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" },
#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \
reg, reg_kind, reg_flags, \
diff --git a/src/compiler/codegen/x86/X86/Factory.cc b/src/compiler/codegen/x86/X86/Factory.cc
index 9538931..291b761 100644
--- a/src/compiler/codegen/x86/X86/Factory.cc
+++ b/src/compiler/codegen/x86/X86/Factory.cc
@@ -105,6 +105,7 @@
if (value == 0) {
res = newLIR2(cUnit, kX86Xor32RR, rDest, rDest);
} else {
+ // Note, there is no byte immediate form of a 32 bit immediate move.
res = newLIR2(cUnit, kX86Mov32RI, rDest, value);
}
diff --git a/src/compiler/codegen/x86/X86/Gen.cc b/src/compiler/codegen/x86/X86/Gen.cc
index fb8bcd7..28c6914 100644
--- a/src/compiler/codegen/x86/X86/Gen.cc
+++ b/src/compiler/codegen/x86/X86/Gen.cc
@@ -312,11 +312,11 @@
LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
int checkValue, LIR* target)
{
- if (false && (checkValue == 0) && (cond == kCondEq || cond == kCondNe)) {
+ if ((checkValue == 0) && (cond == kCondEq || cond == kCondNe)) {
// TODO: when checkValue == 0 and reg is rCX, use the jcxz/nz opcode
- // newLIR2(cUnit, kX86Test32RR, reg, reg);
+ newLIR2(cUnit, kX86Test32RR, reg, reg);
} else {
- newLIR2(cUnit, kX86Cmp32RI, reg, checkValue);
+ newLIR2(cUnit, IS_SIMM8(checkValue) ? kX86Cmp32RI8 : kX86Cmp32RI, reg, checkValue);
}
X86ConditionCode cc = oatX86ConditionEncoding(cond);
LIR* branch = newLIR2(cUnit, kX86Jcc8, 0 /* lir operand for Jcc offset */ , cc);
diff --git a/src/compiler/codegen/x86/X86LIR.h b/src/compiler/codegen/x86/X86LIR.h
index 9872313..43fc63c 100644
--- a/src/compiler/codegen/x86/X86LIR.h
+++ b/src/compiler/codegen/x86/X86LIR.h
@@ -402,6 +402,7 @@
opcode ## 16 ## reg, opcode ## 16 ## mem, opcode ## 16 ## array, \
opcode ## 32 ## reg, opcode ## 32 ## mem, opcode ## 32 ## array
UnaryOpcode(kX86Test, RI, MI, AI),
+ kX86Test32RR,
UnaryOpcode(kX86Not, R, M, A),
UnaryOpcode(kX86Neg, R, M, A),
UnaryOpcode(kX86Mul, DaR, DaM, DaA),