MIPS64: Implement HSelect
Test: mma test-art-host-gtest
Test: mma test-art-target-gtest in QEMU (MIPS64R6)
Test: ./testrunner.py --target --optimizing in QEMU (MIPS64R6)
Change-Id: I633fc479e0ca61b7d49b4c36fbe5db9a94da535d
diff --git a/compiler/optimizing/code_generator_mips64.h b/compiler/optimizing/code_generator_mips64.h
index d03a9ea..72d4743 100644
--- a/compiler/optimizing/code_generator_mips64.h
+++ b/compiler/optimizing/code_generator_mips64.h
@@ -293,6 +293,13 @@
void GenerateDivRemWithAnyConstant(HBinaryOperation* instruction);
void GenerateDivRemIntegral(HBinaryOperation* instruction);
void GenerateIntLongCompare(IfCondition cond, bool is64bit, LocationSummary* locations);
+ // When the function returns `false` it means that the condition holds if `dst` is non-zero
+ // and doesn't hold if `dst` is zero. If it returns `true`, the roles of zero and non-zero
+ // `dst` are exchanged.
+ bool MaterializeIntLongCompare(IfCondition cond,
+ bool is64bit,
+ LocationSummary* input_locations,
+ GpuRegister dst);
void GenerateIntLongCompareAndBranch(IfCondition cond,
bool is64bit,
LocationSummary* locations,
@@ -301,6 +308,14 @@
bool gt_bias,
Primitive::Type type,
LocationSummary* locations);
+ // When the function returns `false` it means that the condition holds if `dst` is non-zero
+ // and doesn't hold if `dst` is zero. If it returns `true`, the roles of zero and non-zero
+ // `dst` are exchanged.
+ bool MaterializeFpCompare(IfCondition cond,
+ bool gt_bias,
+ Primitive::Type type,
+ LocationSummary* input_locations,
+ FpuRegister dst);
void GenerateFpCompareAndBranch(IfCondition cond,
bool gt_bias,
Primitive::Type type,
@@ -320,6 +335,7 @@
int32_t VecAddress(LocationSummary* locations,
size_t size,
/* out */ GpuRegister* adjusted_base);
+ void GenConditionalMove(HSelect* select);
Mips64Assembler* const assembler_;
CodeGeneratorMIPS64* const codegen_;