Fix cpplint whitespace/braces issues
Change-Id: Ide80939faf8e8690d8842dde8133902ac725ed1a
diff --git a/compiler/dex/quick/mips/assemble_mips.cc b/compiler/dex/quick/mips/assemble_mips.cc
index 2482aa4..dcfb13f 100644
--- a/compiler/dex/quick/mips/assemble_mips.cc
+++ b/compiler/dex/quick/mips/assemble_mips.cc
@@ -457,8 +457,7 @@
* NOTE: An out-of-range bal isn't supported because it should
* never happen with the current PIC model.
*/
-void MipsMir2Lir::ConvertShortToLongBranch(LIR* lir)
-{
+void MipsMir2Lir::ConvertShortToLongBranch(LIR* lir) {
// For conditional branches we'll need to reverse the sense
bool unconditional = false;
int opcode = lir->opcode;
@@ -513,8 +512,7 @@
* instruction. In those cases we will try to substitute a new code
* sequence or request that the trace be shortened and retried.
*/
-AssemblerStatus MipsMir2Lir::AssembleInstructions(uintptr_t start_addr)
-{
+AssemblerStatus MipsMir2Lir::AssembleInstructions(uintptr_t start_addr) {
LIR *lir;
AssemblerStatus res = kSuccess; // Assume success
@@ -708,8 +706,7 @@
return res;
}
-int MipsMir2Lir::GetInsnSize(LIR* lir)
-{
+int MipsMir2Lir::GetInsnSize(LIR* lir) {
return EncodingMap[lir->opcode].size;
}
diff --git a/compiler/dex/quick/mips/call_mips.cc b/compiler/dex/quick/mips/call_mips.cc
index eb0302e..db57643 100644
--- a/compiler/dex/quick/mips/call_mips.cc
+++ b/compiler/dex/quick/mips/call_mips.cc
@@ -24,8 +24,7 @@
namespace art {
void MipsMir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir,
- SpecialCaseHandler special_case)
-{
+ SpecialCaseHandler special_case) {
// TODO
}
@@ -61,8 +60,7 @@
*
*/
void MipsMir2Lir::GenSparseSwitch(MIR* mir, uint32_t table_offset,
- RegLocation rl_src)
-{
+ RegLocation rl_src) {
const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
if (cu_->verbose) {
DumpSparseSwitchTable(table);
@@ -142,8 +140,7 @@
* done:
*/
void MipsMir2Lir::GenPackedSwitch(MIR* mir, uint32_t table_offset,
- RegLocation rl_src)
-{
+ RegLocation rl_src) {
const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
if (cu_->verbose) {
DumpPackedSwitchTable(table);
@@ -227,8 +224,7 @@
*
* Total size is 4+(width * size + 1)/2 16-bit code units.
*/
-void MipsMir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src)
-{
+void MipsMir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) {
const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
// Add the table to the list - we'll process it later
FillArrayData *tab_rec =
@@ -270,8 +266,7 @@
/*
* TODO: implement fast path to short-circuit thin-lock case
*/
-void MipsMir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src)
-{
+void MipsMir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) {
FlushAllRegs();
LoadValueDirectFixed(rl_src, rMIPS_ARG0); // Get obj
LockCallTemps(); // Prepare for explicit register usage
@@ -286,8 +281,7 @@
/*
* TODO: implement fast path to short-circuit thin-lock case
*/
-void MipsMir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src)
-{
+void MipsMir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) {
FlushAllRegs();
LoadValueDirectFixed(rl_src, rMIPS_ARG0); // Get obj
LockCallTemps(); // Prepare for explicit register usage
@@ -299,8 +293,7 @@
MarkSafepointPC(call_inst);
}
-void MipsMir2Lir::GenMoveException(RegLocation rl_dest)
-{
+void MipsMir2Lir::GenMoveException(RegLocation rl_dest) {
int ex_offset = Thread::ExceptionOffset().Int32Value();
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
int reset_reg = AllocTemp();
@@ -314,8 +307,7 @@
/*
* Mark garbage collection card. Skip if the value we're storing is null.
*/
-void MipsMir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg)
-{
+void MipsMir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg) {
int reg_card_base = AllocTemp();
int reg_card_no = AllocTemp();
LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL);
@@ -328,8 +320,7 @@
FreeTemp(reg_card_base);
FreeTemp(reg_card_no);
}
-void MipsMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method)
-{
+void MipsMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) {
int spill_count = num_core_spills_ + num_fp_spills_;
/*
* On entry, rMIPS_ARG0, rMIPS_ARG1, rMIPS_ARG2 & rMIPS_ARG3 are live. Let the register
@@ -375,8 +366,7 @@
FreeTemp(rMIPS_ARG3);
}
-void MipsMir2Lir::GenExitSequence()
-{
+void MipsMir2Lir::GenExitSequence() {
/*
* In the exit path, rMIPS_RET0/rMIPS_RET1 are live - make sure they aren't
* allocated by the register utilities as temps.
diff --git a/compiler/dex/quick/mips/fp_mips.cc b/compiler/dex/quick/mips/fp_mips.cc
index 8581d5b..2e744a2 100644
--- a/compiler/dex/quick/mips/fp_mips.cc
+++ b/compiler/dex/quick/mips/fp_mips.cc
@@ -22,8 +22,7 @@
namespace art {
void MipsMir2Lir::GenArithOpFloat(Instruction::Code opcode,
- RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
-{
+ RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
int op = kMipsNop;
RegLocation rl_result;
@@ -69,8 +68,7 @@
}
void MipsMir2Lir::GenArithOpDouble(Instruction::Code opcode,
- RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
-{
+ RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
int op = kMipsNop;
RegLocation rl_result;
@@ -117,8 +115,7 @@
}
void MipsMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest,
- RegLocation rl_src)
-{
+ RegLocation rl_src) {
int op = kMipsNop;
int src_reg;
RegLocation rl_result;
@@ -175,8 +172,7 @@
}
void MipsMir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest,
- RegLocation rl_src1, RegLocation rl_src2)
-{
+ RegLocation rl_src1, RegLocation rl_src2) {
bool wide = true;
int offset = -1; // Make gcc happy.
@@ -215,13 +211,11 @@
}
void MipsMir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir,
- bool gt_bias, bool is_double)
-{
+ bool gt_bias, bool is_double) {
UNIMPLEMENTED(FATAL) << "Need codegen for fused fp cmp branch";
}
-void MipsMir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src)
-{
+void MipsMir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src) {
RegLocation rl_result;
rl_src = LoadValue(rl_src, kCoreReg);
rl_result = EvalLoc(rl_dest, kCoreReg, true);
@@ -229,8 +223,7 @@
StoreValue(rl_dest, rl_result);
}
-void MipsMir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src)
-{
+void MipsMir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src) {
RegLocation rl_result;
rl_src = LoadValueWide(rl_src, kCoreReg);
rl_result = EvalLoc(rl_dest, kCoreReg, true);
@@ -239,8 +232,7 @@
StoreValueWide(rl_dest, rl_result);
}
-bool MipsMir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min)
-{
+bool MipsMir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min) {
// TODO: need Mips implementation
return false;
}
diff --git a/compiler/dex/quick/mips/int_mips.cc b/compiler/dex/quick/mips/int_mips.cc
index 8bfc4e1..03a58cc 100644
--- a/compiler/dex/quick/mips/int_mips.cc
+++ b/compiler/dex/quick/mips/int_mips.cc
@@ -41,8 +41,7 @@
*
*/
void MipsMir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
rl_src1 = LoadValueWide(rl_src1, kCoreReg);
rl_src2 = LoadValueWide(rl_src2, kCoreReg);
int t0 = AllocTemp();
@@ -63,8 +62,7 @@
}
LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, int src1, int src2,
- LIR* target)
-{
+ LIR* target) {
LIR* branch;
MipsOpCode slt_op;
MipsOpCode br_op;
@@ -131,8 +129,7 @@
}
LIR* MipsMir2Lir::OpCmpImmBranch(ConditionCode cond, int reg,
- int check_value, LIR* target)
-{
+ int check_value, LIR* target) {
LIR* branch;
if (check_value != 0) {
// TUNING: handle s16 & kCondLt/Mi case using slti
@@ -164,8 +161,7 @@
return branch;
}
-LIR* MipsMir2Lir::OpRegCopyNoInsert(int r_dest, int r_src)
-{
+LIR* MipsMir2Lir::OpRegCopyNoInsert(int r_dest, int r_src) {
if (MIPS_FPREG(r_dest) || MIPS_FPREG(r_src))
return OpFpRegCopy(r_dest, r_src);
LIR* res = RawLIR(current_dalvik_offset_, kMipsMove,
@@ -176,16 +172,14 @@
return res;
}
-LIR* MipsMir2Lir::OpRegCopy(int r_dest, int r_src)
-{
+LIR* MipsMir2Lir::OpRegCopy(int r_dest, int r_src) {
LIR *res = OpRegCopyNoInsert(r_dest, r_src);
AppendLIR(res);
return res;
}
void MipsMir2Lir::OpRegCopyWide(int dest_lo, int dest_hi, int src_lo,
- int src_hi)
-{
+ int src_hi) {
bool dest_fp = MIPS_FPREG(dest_lo) && MIPS_FPREG(dest_hi);
bool src_fp = MIPS_FPREG(src_lo) && MIPS_FPREG(src_hi);
assert(MIPS_FPREG(src_lo) == MIPS_FPREG(src_hi));
@@ -215,26 +209,22 @@
}
}
-void MipsMir2Lir::GenSelect(BasicBlock* bb, MIR* mir)
-{
+void MipsMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {
UNIMPLEMENTED(FATAL) << "Need codegen for select";
}
-void MipsMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir)
-{
+void MipsMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) {
UNIMPLEMENTED(FATAL) << "Need codegen for fused long cmp branch";
}
LIR* MipsMir2Lir::GenRegMemCheck(ConditionCode c_code,
- int reg1, int base, int offset, ThrowKind kind)
-{
+ int reg1, int base, int offset, ThrowKind kind) {
LOG(FATAL) << "Unexpected use of GenRegMemCheck for Arm";
return NULL;
}
RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, int reg1, int reg2,
- bool is_div)
-{
+ bool is_div) {
NewLIR4(kMipsDiv, r_HI, r_LO, reg1, reg2);
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
if (is_div) {
@@ -246,8 +236,7 @@
}
RegLocation MipsMir2Lir::GenDivRemLit(RegLocation rl_dest, int reg1, int lit,
- bool is_div)
-{
+ bool is_div) {
int t_reg = AllocTemp();
NewLIR3(kMipsAddiu, t_reg, r_ZERO, lit);
NewLIR4(kMipsDiv, r_HI, r_LO, reg1, t_reg);
@@ -261,13 +250,11 @@
return rl_result;
}
-void MipsMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset)
-{
+void MipsMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) {
LOG(FATAL) << "Unexpected use of OpLea for Arm";
}
-void MipsMir2Lir::OpTlsCmp(int offset, int val)
-{
+void MipsMir2Lir::OpTlsCmp(int offset, int val) {
LOG(FATAL) << "Unexpected use of OpTlsCmp for Arm";
}
@@ -286,22 +273,19 @@
return NULL;
}
-LIR* MipsMir2Lir::OpVldm(int rBase, int count)
-{
+LIR* MipsMir2Lir::OpVldm(int rBase, int count) {
LOG(FATAL) << "Unexpected use of OpVldm for Mips";
return NULL;
}
-LIR* MipsMir2Lir::OpVstm(int rBase, int count)
-{
+LIR* MipsMir2Lir::OpVstm(int rBase, int count) {
LOG(FATAL) << "Unexpected use of OpVstm for Mips";
return NULL;
}
void MipsMir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src,
RegLocation rl_result, int lit,
- int first_bit, int second_bit)
-{
+ int first_bit, int second_bit) {
int t_reg = AllocTemp();
OpRegRegImm(kOpLsl, t_reg, rl_src.low_reg, second_bit - first_bit);
OpRegRegReg(kOpAdd, rl_result.low_reg, rl_src.low_reg, t_reg);
@@ -311,8 +295,7 @@
}
}
-void MipsMir2Lir::GenDivZeroCheck(int reg_lo, int reg_hi)
-{
+void MipsMir2Lir::GenDivZeroCheck(int reg_lo, int reg_hi) {
int t_reg = AllocTemp();
OpRegRegReg(kOpOr, t_reg, reg_lo, reg_hi);
GenImmedCheck(kCondEq, t_reg, 0, kThrowDivZero);
@@ -320,41 +303,35 @@
}
// Test suspend flag, return target of taken suspend branch
-LIR* MipsMir2Lir::OpTestSuspend(LIR* target)
-{
+LIR* MipsMir2Lir::OpTestSuspend(LIR* target) {
OpRegImm(kOpSub, rMIPS_SUSPEND, 1);
return OpCmpImmBranch((target == NULL) ? kCondEq : kCondNe, rMIPS_SUSPEND, 0, target);
}
// Decrement register and branch on condition
-LIR* MipsMir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target)
-{
+LIR* MipsMir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) {
OpRegImm(kOpSub, reg, 1);
return OpCmpImmBranch(c_code, reg, 0, target);
}
bool MipsMir2Lir::SmallLiteralDivide(Instruction::Code dalvik_opcode,
- RegLocation rl_src, RegLocation rl_dest, int lit)
-{
+ RegLocation rl_src, RegLocation rl_dest, int lit) {
LOG(FATAL) << "Unexpected use of smallLiteralDive in Mips";
return false;
}
-LIR* MipsMir2Lir::OpIT(ConditionCode cond, const char* guide)
-{
+LIR* MipsMir2Lir::OpIT(ConditionCode cond, const char* guide) {
LOG(FATAL) << "Unexpected use of OpIT in Mips";
return NULL;
}
void MipsMir2Lir::GenMulLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
LOG(FATAL) << "Unexpected use of GenMulLong for Mips";
}
void MipsMir2Lir::GenAddLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
rl_src1 = LoadValueWide(rl_src1, kCoreReg);
rl_src2 = LoadValueWide(rl_src2, kCoreReg);
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
@@ -376,8 +353,7 @@
}
void MipsMir2Lir::GenSubLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
rl_src1 = LoadValueWide(rl_src1, kCoreReg);
rl_src2 = LoadValueWide(rl_src2, kCoreReg);
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
@@ -398,8 +374,7 @@
StoreValueWide(rl_dest, rl_result);
}
-void MipsMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src)
-{
+void MipsMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) {
rl_src = LoadValueWide(rl_src, kCoreReg);
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
/*
@@ -420,20 +395,17 @@
}
void MipsMir2Lir::GenAndLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
LOG(FATAL) << "Unexpected use of GenAndLong for Mips";
}
void MipsMir2Lir::GenOrLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
LOG(FATAL) << "Unexpected use of GenOrLong for Mips";
}
void MipsMir2Lir::GenXorLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
LOG(FATAL) << "Unexpected use of GenXorLong for Mips";
}
@@ -441,8 +413,7 @@
* Generate array load
*/
void MipsMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
- RegLocation rl_index, RegLocation rl_dest, int scale)
-{
+ RegLocation rl_index, RegLocation rl_dest, int scale) {
RegisterClass reg_class = oat_reg_class_by_size(size);
int len_offset = mirror::Array::LengthOffset().Int32Value();
int data_offset;
@@ -513,8 +484,7 @@
*
*/
void MipsMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
- RegLocation rl_index, RegLocation rl_src, int scale)
-{
+ RegLocation rl_index, RegLocation rl_src, int scale) {
RegisterClass reg_class = oat_reg_class_by_size(size);
int len_offset = mirror::Array::LengthOffset().Int32Value();
int data_offset;
@@ -586,8 +556,7 @@
*
*/
void MipsMir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array,
- RegLocation rl_index, RegLocation rl_src, int scale)
-{
+ RegLocation rl_index, RegLocation rl_src, int scale) {
int len_offset = mirror::Array::LengthOffset().Int32Value();
int data_offset = mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value();
@@ -643,15 +612,13 @@
}
void MipsMir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
- RegLocation rl_src1, RegLocation rl_shift)
-{
+ RegLocation rl_src1, RegLocation rl_shift) {
// Default implementation is just to ignore the constant case.
GenShiftOpLong(opcode, rl_dest, rl_src1, rl_shift);
}
void MipsMir2Lir::GenArithImmOpLong(Instruction::Code opcode,
- RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
-{
+ RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
// Default - bail to non-const handler.
GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2);
}
diff --git a/compiler/dex/quick/mips/target_mips.cc b/compiler/dex/quick/mips/target_mips.cc
index cab2c1b..bd20e00 100644
--- a/compiler/dex/quick/mips/target_mips.cc
+++ b/compiler/dex/quick/mips/target_mips.cc
@@ -36,26 +36,22 @@
static int fp_temps[] = {r_F0, r_F1, r_F2, r_F3, r_F4, r_F5, r_F6, r_F7,
r_F8, r_F9, r_F10, r_F11, r_F12, r_F13, r_F14, r_F15};
-RegLocation MipsMir2Lir::LocCReturn()
-{
+RegLocation MipsMir2Lir::LocCReturn() {
RegLocation res = MIPS_LOC_C_RETURN;
return res;
}
-RegLocation MipsMir2Lir::LocCReturnWide()
-{
+RegLocation MipsMir2Lir::LocCReturnWide() {
RegLocation res = MIPS_LOC_C_RETURN_WIDE;
return res;
}
-RegLocation MipsMir2Lir::LocCReturnFloat()
-{
+RegLocation MipsMir2Lir::LocCReturnFloat() {
RegLocation res = MIPS_LOC_C_RETURN_FLOAT;
return res;
}
-RegLocation MipsMir2Lir::LocCReturnDouble()
-{
+RegLocation MipsMir2Lir::LocCReturnDouble() {
RegLocation res = MIPS_LOC_C_RETURN_DOUBLE;
return res;
}
@@ -86,28 +82,24 @@
}
// Create a double from a pair of singles.
-int MipsMir2Lir::S2d(int low_reg, int high_reg)
-{
+int MipsMir2Lir::S2d(int low_reg, int high_reg) {
return MIPS_S2D(low_reg, high_reg);
}
// Return mask to strip off fp reg flags and bias.
-uint32_t MipsMir2Lir::FpRegMask()
-{
+uint32_t MipsMir2Lir::FpRegMask() {
return MIPS_FP_REG_MASK;
}
// True if both regs single, both core or both double.
-bool MipsMir2Lir::SameRegType(int reg1, int reg2)
-{
+bool MipsMir2Lir::SameRegType(int reg1, int reg2) {
return (MIPS_REGTYPE(reg1) == MIPS_REGTYPE(reg2));
}
/*
* Decode the register id.
*/
-uint64_t MipsMir2Lir::GetRegMaskCommon(int reg)
-{
+uint64_t MipsMir2Lir::GetRegMaskCommon(int reg) {
uint64_t seed;
int shift;
int reg_id;
@@ -123,14 +115,12 @@
return (seed << shift);
}
-uint64_t MipsMir2Lir::GetPCUseDefEncoding()
-{
+uint64_t MipsMir2Lir::GetPCUseDefEncoding() {
return ENCODE_MIPS_REG_PC;
}
-void MipsMir2Lir::SetupTargetResourceMasks(LIR* lir)
-{
+void MipsMir2Lir::SetupTargetResourceMasks(LIR* lir) {
DCHECK_EQ(cu_->instruction_set, kMips);
// Mips-specific resource map setup here.
@@ -162,8 +152,7 @@
* Interpret a format string and build a string no longer than size
* See format key in Assemble.c.
*/
-std::string MipsMir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr)
-{
+std::string MipsMir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) {
std::string buf;
int i;
const char *fmt_end = &fmt[strlen(fmt)];
@@ -255,8 +244,7 @@
}
// FIXME: need to redo resource maps for MIPS - fix this at that time
-void MipsMir2Lir::DumpResourceMask(LIR *mips_lir, uint64_t mask, const char *prefix)
-{
+void MipsMir2Lir::DumpResourceMask(LIR *mips_lir, uint64_t mask, const char *prefix) {
char buf[256];
buf[0] = 0;
@@ -306,8 +294,7 @@
* machinery is in place, always spill lr.
*/
-void MipsMir2Lir::AdjustSpillMask()
-{
+void MipsMir2Lir::AdjustSpillMask() {
core_spill_mask_ |= (1 << r_RA);
num_core_spills_++;
}
@@ -318,13 +305,11 @@
* include any holes in the mask. Associate holes with
* Dalvik register INVALID_VREG (0xFFFFU).
*/
-void MipsMir2Lir::MarkPreservedSingle(int s_reg, int reg)
-{
+void MipsMir2Lir::MarkPreservedSingle(int s_reg, int reg) {
LOG(FATAL) << "No support yet for promoted FP regs";
}
-void MipsMir2Lir::FlushRegWide(int reg1, int reg2)
-{
+void MipsMir2Lir::FlushRegWide(int reg1, int reg2) {
RegisterInfo* info1 = GetRegInfo(reg1);
RegisterInfo* info2 = GetRegInfo(reg2);
DCHECK(info1 && info2 && info1->pair && info2->pair &&
@@ -345,8 +330,7 @@
}
}
-void MipsMir2Lir::FlushReg(int reg)
-{
+void MipsMir2Lir::FlushReg(int reg) {
RegisterInfo* info = GetRegInfo(reg);
if (info->live && info->dirty) {
info->dirty = false;
@@ -361,8 +345,7 @@
}
/* Clobber all regs that might be used by an external C call */
-void MipsMir2Lir::ClobberCalleeSave()
-{
+void MipsMir2Lir::ClobberCalleeSave() {
Clobber(r_ZERO);
Clobber(r_AT);
Clobber(r_V0);
@@ -404,29 +387,25 @@
Clobber(r_F15);
}
-RegLocation MipsMir2Lir::GetReturnWideAlt()
-{
+RegLocation MipsMir2Lir::GetReturnWideAlt() {
UNIMPLEMENTED(FATAL) << "No GetReturnWideAlt for MIPS";
RegLocation res = LocCReturnWide();
return res;
}
-RegLocation MipsMir2Lir::GetReturnAlt()
-{
+RegLocation MipsMir2Lir::GetReturnAlt() {
UNIMPLEMENTED(FATAL) << "No GetReturnAlt for MIPS";
RegLocation res = LocCReturn();
return res;
}
-MipsMir2Lir::RegisterInfo* MipsMir2Lir::GetRegInfo(int reg)
-{
+MipsMir2Lir::RegisterInfo* MipsMir2Lir::GetRegInfo(int reg) {
return MIPS_FPREG(reg) ? ®_pool_->FPRegs[reg & MIPS_FP_REG_MASK]
: ®_pool_->core_regs[reg];
}
/* To be used when explicitly managing register use */
-void MipsMir2Lir::LockCallTemps()
-{
+void MipsMir2Lir::LockCallTemps() {
LockTemp(rMIPS_ARG0);
LockTemp(rMIPS_ARG1);
LockTemp(rMIPS_ARG2);
@@ -434,16 +413,14 @@
}
/* To be used when explicitly managing register use */
-void MipsMir2Lir::FreeCallTemps()
-{
+void MipsMir2Lir::FreeCallTemps() {
FreeTemp(rMIPS_ARG0);
FreeTemp(rMIPS_ARG1);
FreeTemp(rMIPS_ARG2);
FreeTemp(rMIPS_ARG3);
}
-void MipsMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind)
-{
+void MipsMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) {
#if ANDROID_SMP != 0
NewLIR1(kMipsSync, 0 /* Only stype currently supported */);
#endif
@@ -454,8 +431,7 @@
* high reg in next byte.
*/
int MipsMir2Lir::AllocTypedTempPair(bool fp_hint,
- int reg_class)
-{
+ int reg_class) {
int high_reg;
int low_reg;
int res = 0;
@@ -473,17 +449,14 @@
return res;
}
-int MipsMir2Lir::AllocTypedTemp(bool fp_hint, int reg_class)
-{
- if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg))
-{
+int MipsMir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) {
+ if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
return AllocTempFloat();
}
return AllocTemp();
}
-void MipsMir2Lir::CompilerInitializeRegAlloc()
-{
+void MipsMir2Lir::CompilerInitializeRegAlloc() {
int num_regs = sizeof(core_regs)/sizeof(*core_regs);
int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs);
int num_temps = sizeof(core_temps)/sizeof(*core_temps);
@@ -518,8 +491,7 @@
}
}
-void MipsMir2Lir::FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free)
-{
+void MipsMir2Lir::FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) {
if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) &&
(rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) {
// No overlap, free both
@@ -533,14 +505,12 @@
* ensure that all branch instructions can be restarted if
* there is a trap in the shadow. Allocate a temp register.
*/
-int MipsMir2Lir::LoadHelper(int offset)
-{
+int MipsMir2Lir::LoadHelper(int offset) {
LoadWordDisp(rMIPS_SELF, offset, r_T9);
return r_T9;
}
-void MipsMir2Lir::SpillCoreRegs()
-{
+void MipsMir2Lir::SpillCoreRegs() {
if (num_core_spills_ == 0) {
return;
}
@@ -555,8 +525,7 @@
}
}
-void MipsMir2Lir::UnSpillCoreRegs()
-{
+void MipsMir2Lir::UnSpillCoreRegs() {
if (num_core_spills_ == 0) {
return;
}
@@ -571,8 +540,7 @@
OpRegImm(kOpAdd, rMIPS_SP, frame_size_);
}
-bool MipsMir2Lir::IsUnconditionalBranch(LIR* lir)
-{
+bool MipsMir2Lir::IsUnconditionalBranch(LIR* lir) {
return (lir->opcode == kMipsB);
}
@@ -592,18 +560,15 @@
return new MipsMir2Lir(cu, mir_graph, arena);
}
-uint64_t MipsMir2Lir::GetTargetInstFlags(int opcode)
-{
+uint64_t MipsMir2Lir::GetTargetInstFlags(int opcode) {
return MipsMir2Lir::EncodingMap[opcode].flags;
}
-const char* MipsMir2Lir::GetTargetInstName(int opcode)
-{
+const char* MipsMir2Lir::GetTargetInstName(int opcode) {
return MipsMir2Lir::EncodingMap[opcode].name;
}
-const char* MipsMir2Lir::GetTargetInstFmt(int opcode)
-{
+const char* MipsMir2Lir::GetTargetInstFmt(int opcode) {
return MipsMir2Lir::EncodingMap[opcode].fmt;
}
diff --git a/compiler/dex/quick/mips/utility_mips.cc b/compiler/dex/quick/mips/utility_mips.cc
index 8daafc8..089764f 100644
--- a/compiler/dex/quick/mips/utility_mips.cc
+++ b/compiler/dex/quick/mips/utility_mips.cc
@@ -21,8 +21,7 @@
namespace art {
/* This file contains codegen for the MIPS32 ISA. */
-LIR* MipsMir2Lir::OpFpRegCopy(int r_dest, int r_src)
-{
+LIR* MipsMir2Lir::OpFpRegCopy(int r_dest, int r_src) {
int opcode;
/* must be both DOUBLE or both not DOUBLE */
DCHECK_EQ(MIPS_DOUBLEREG(r_dest),MIPS_DOUBLEREG(r_src));
@@ -51,23 +50,19 @@
return res;
}
-bool MipsMir2Lir::InexpensiveConstantInt(int32_t value)
-{
+bool MipsMir2Lir::InexpensiveConstantInt(int32_t value) {
return ((value == 0) || IsUint(16, value) || ((value < 0) && (value >= -32768)));
}
-bool MipsMir2Lir::InexpensiveConstantFloat(int32_t value)
-{
+bool MipsMir2Lir::InexpensiveConstantFloat(int32_t value) {
return false; // TUNING
}
-bool MipsMir2Lir::InexpensiveConstantLong(int64_t value)
-{
+bool MipsMir2Lir::InexpensiveConstantLong(int64_t value) {
return false; // TUNING
}
-bool MipsMir2Lir::InexpensiveConstantDouble(int64_t value)
-{
+bool MipsMir2Lir::InexpensiveConstantDouble(int64_t value) {
return false; // TUNING
}
@@ -80,8 +75,7 @@
* 1) r_dest is freshly returned from AllocTemp or
* 2) The codegen is under fixed register usage
*/
-LIR* MipsMir2Lir::LoadConstantNoClobber(int r_dest, int value)
-{
+LIR* MipsMir2Lir::LoadConstantNoClobber(int r_dest, int value) {
LIR *res;
int r_dest_save = r_dest;
@@ -112,15 +106,13 @@
return res;
}
-LIR* MipsMir2Lir::OpUnconditionalBranch(LIR* target)
-{
+LIR* MipsMir2Lir::OpUnconditionalBranch(LIR* target) {
LIR* res = NewLIR1(kMipsB, 0 /* offset to be patched during assembly*/ );
res->target = target;
return res;
}
-LIR* MipsMir2Lir::OpReg(OpKind op, int r_dest_src)
-{
+LIR* MipsMir2Lir::OpReg(OpKind op, int r_dest_src) {
MipsOpCode opcode = kMipsNop;
switch (op) {
case kOpBlx:
@@ -136,8 +128,7 @@
}
LIR* MipsMir2Lir::OpRegImm(OpKind op, int r_dest_src1,
- int value)
-{
+ int value) {
LIR *res;
bool neg = (value < 0);
int abs_value = (neg) ? -value : value;
@@ -167,8 +158,7 @@
return res;
}
-LIR* MipsMir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2)
-{
+LIR* MipsMir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2) {
MipsOpCode opcode = kMipsNop;
switch (op) {
case kOpAdd:
@@ -209,8 +199,7 @@
return NewLIR3(opcode, r_dest, r_src1, r_src2);
}
-LIR* MipsMir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src1, int value)
-{
+LIR* MipsMir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src1, int value) {
LIR *res;
MipsOpCode opcode = kMipsNop;
bool short_form = true;
@@ -298,8 +287,7 @@
return res;
}
-LIR* MipsMir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2)
-{
+LIR* MipsMir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2) {
MipsOpCode opcode = kMipsNop;
LIR *res;
switch (op) {
@@ -342,8 +330,7 @@
return NewLIR2(opcode, r_dest_src1, r_src2);
}
-LIR* MipsMir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value)
-{
+LIR* MipsMir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) {
LIR *res;
res = LoadConstantNoClobber(r_dest_lo, Low32Bits(value));
LoadConstantNoClobber(r_dest_hi, High32Bits(value));
@@ -352,8 +339,7 @@
/* Load value from base + scaled index. */
LIR* MipsMir2Lir::LoadBaseIndexed(int rBase, int r_index, int r_dest,
- int scale, OpSize size)
-{
+ int scale, OpSize size) {
LIR *first = NULL;
LIR *res;
MipsOpCode opcode = kMipsNop;
@@ -405,8 +391,7 @@
/* store value base base + scaled index. */
LIR* MipsMir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src,
- int scale, OpSize size)
-{
+ int scale, OpSize size) {
LIR *first = NULL;
MipsOpCode opcode = kMipsNop;
int r_new_index = r_index;
@@ -452,7 +437,7 @@
}
LIR* MipsMir2Lir::LoadBaseDispBody(int rBase, int displacement, int r_dest,
- int r_dest_hi, OpSize size, int s_reg)
+ int r_dest_hi, OpSize size, int s_reg) {
/*
* Load value from base + displacement. Optionally perform null check
* on base (which must have an associated s_reg and MIR). If not
@@ -461,7 +446,6 @@
* and base and dest are the same, spill some other register to
* rlp and then restore.
*/
-{
LIR *res;
LIR *load = NULL;
LIR *load2 = NULL;
@@ -551,21 +535,18 @@
}
LIR* MipsMir2Lir::LoadBaseDisp(int rBase, int displacement, int r_dest,
- OpSize size, int s_reg)
-{
+ OpSize size, int s_reg) {
return LoadBaseDispBody(rBase, displacement, r_dest, -1,
size, s_reg);
}
LIR* MipsMir2Lir::LoadBaseDispWide(int rBase, int displacement,
- int r_dest_lo, int r_dest_hi, int s_reg)
-{
+ int r_dest_lo, int r_dest_hi, int s_reg) {
return LoadBaseDispBody(rBase, displacement, r_dest_lo, r_dest_hi, kLong, s_reg);
}
LIR* MipsMir2Lir::StoreBaseDispBody(int rBase, int displacement,
- int r_src, int r_src_hi, OpSize size)
-{
+ int r_src, int r_src_hi, OpSize size) {
LIR *res;
LIR *store = NULL;
LIR *store2 = NULL;
@@ -647,52 +628,44 @@
}
LIR* MipsMir2Lir::StoreBaseDisp(int rBase, int displacement, int r_src,
- OpSize size)
-{
+ OpSize size) {
return StoreBaseDispBody(rBase, displacement, r_src, -1, size);
}
LIR* MipsMir2Lir::StoreBaseDispWide(int rBase, int displacement,
- int r_src_lo, int r_src_hi)
-{
+ int r_src_lo, int r_src_hi) {
return StoreBaseDispBody(rBase, displacement, r_src_lo, r_src_hi, kLong);
}
-LIR* MipsMir2Lir::OpThreadMem(OpKind op, int thread_offset)
-{
+LIR* MipsMir2Lir::OpThreadMem(OpKind op, int thread_offset) {
LOG(FATAL) << "Unexpected use of OpThreadMem for MIPS";
return NULL;
}
-LIR* MipsMir2Lir::OpMem(OpKind op, int rBase, int disp)
-{
+LIR* MipsMir2Lir::OpMem(OpKind op, int rBase, int disp) {
LOG(FATAL) << "Unexpected use of OpMem for MIPS";
return NULL;
}
LIR* MipsMir2Lir::StoreBaseIndexedDisp( int rBase, int r_index, int scale, int displacement,
- int r_src, int r_src_hi, OpSize size, int s_reg)
-{
+ int r_src, int r_src_hi, OpSize size, int s_reg) {
LOG(FATAL) << "Unexpected use of StoreBaseIndexedDisp for MIPS";
return NULL;
}
LIR* MipsMir2Lir::OpRegMem(OpKind op, int r_dest, int rBase,
- int offset)
-{
+ int offset) {
LOG(FATAL) << "Unexpected use of OpRegMem for MIPS";
return NULL;
}
LIR* MipsMir2Lir::LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
- int r_dest, int r_dest_hi, OpSize size, int s_reg)
-{
+ int r_dest, int r_dest_hi, OpSize size, int s_reg) {
LOG(FATAL) << "Unexpected use of LoadBaseIndexedDisp for MIPS";
return NULL;
}
-LIR* MipsMir2Lir::OpCondBranch(ConditionCode cc, LIR* target)
-{
+LIR* MipsMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {
LOG(FATAL) << "Unexpected use of OpCondBranch for MIPS";
return NULL;
}