Fix cpplint whitespace/braces issues
Change-Id: Ide80939faf8e8690d8842dde8133902ac725ed1a
diff --git a/compiler/dex/quick/arm/assemble_arm.cc b/compiler/dex/quick/arm/assemble_arm.cc
index e804215..9e14457 100644
--- a/compiler/dex/quick/arm/assemble_arm.cc
+++ b/compiler/dex/quick/arm/assemble_arm.cc
@@ -1002,8 +1002,7 @@
* discover that pc-relative displacements may not fit the selected
* instruction.
*/
-AssemblerStatus ArmMir2Lir::AssembleInstructions(uintptr_t start_addr)
-{
+AssemblerStatus ArmMir2Lir::AssembleInstructions(uintptr_t start_addr) {
LIR* lir;
AssemblerStatus res = kSuccess; // Assume success
@@ -1389,8 +1388,7 @@
return res;
}
-int ArmMir2Lir::GetInsnSize(LIR* lir)
-{
+int ArmMir2Lir::GetInsnSize(LIR* lir) {
return EncodingMap[lir->opcode].size;
}
diff --git a/compiler/dex/quick/arm/call_arm.cc b/compiler/dex/quick/arm/call_arm.cc
index a6720ce..0e81324 100644
--- a/compiler/dex/quick/arm/call_arm.cc
+++ b/compiler/dex/quick/arm/call_arm.cc
@@ -25,8 +25,7 @@
/* Return the position of an ssa name within the argument list */
-int ArmMir2Lir::InPosition(int s_reg)
-{
+int ArmMir2Lir::InPosition(int s_reg) {
int v_reg = mir_graph_->SRegToVReg(s_reg);
return v_reg - cu_->num_regs;
}
@@ -36,8 +35,7 @@
* there. NOTE: all live arg registers must be locked prior to this call
* to avoid having them allocated as a temp by downstream utilities.
*/
-RegLocation ArmMir2Lir::ArgLoc(RegLocation loc)
-{
+RegLocation ArmMir2Lir::ArgLoc(RegLocation loc) {
int arg_num = InPosition(loc.s_reg_low);
if (loc.wide) {
if (arg_num == 2) {
@@ -66,8 +64,7 @@
* the frame, we can't use the normal LoadValue() because it assumed
* a proper frame - and we're frameless.
*/
-RegLocation ArmMir2Lir::LoadArg(RegLocation loc)
-{
+RegLocation ArmMir2Lir::LoadArg(RegLocation loc) {
if (loc.location == kLocDalvikFrame) {
int start = (InPosition(loc.s_reg_low) + 1) * sizeof(uint32_t);
loc.low_reg = AllocTemp();
@@ -82,8 +79,7 @@
}
/* Lock any referenced arguments that arrive in registers */
-void ArmMir2Lir::LockLiveArgs(MIR* mir)
-{
+void ArmMir2Lir::LockLiveArgs(MIR* mir) {
int first_in = cu_->num_regs;
const int num_arg_regs = 3; // TODO: generalize & move to RegUtil.cc
for (int i = 0; i < mir->ssa_rep->num_uses; i++) {
@@ -97,8 +93,7 @@
/* Find the next MIR, which may be in a following basic block */
// TODO: should this be a utility in mir_graph?
-MIR* ArmMir2Lir::GetNextMir(BasicBlock** p_bb, MIR* mir)
-{
+MIR* ArmMir2Lir::GetNextMir(BasicBlock** p_bb, MIR* mir) {
BasicBlock* bb = *p_bb;
MIR* orig_mir = mir;
while (bb != NULL) {
@@ -123,8 +118,7 @@
/* Used for the "verbose" listing */
//TODO: move to common code
-void ArmMir2Lir::GenPrintLabel(MIR* mir)
-{
+void ArmMir2Lir::GenPrintLabel(MIR* mir) {
/* Mark the beginning of a Dalvik instruction for line tracking */
char* inst_str = cu_->verbose ?
mir_graph_->GetDalvikDisassembly(mir) : NULL;
@@ -132,8 +126,7 @@
}
MIR* ArmMir2Lir::SpecialIGet(BasicBlock** bb, MIR* mir,
- OpSize size, bool long_or_double, bool is_object)
-{
+ OpSize size, bool long_or_double, bool is_object) {
int field_offset;
bool is_volatile;
uint32_t field_idx = mir->dalvikInsn.vC;
@@ -158,8 +151,7 @@
}
MIR* ArmMir2Lir::SpecialIPut(BasicBlock** bb, MIR* mir,
- OpSize size, bool long_or_double, bool is_object)
-{
+ OpSize size, bool long_or_double, bool is_object) {
int field_offset;
bool is_volatile;
uint32_t field_idx = mir->dalvikInsn.vC;
@@ -192,8 +184,7 @@
return GetNextMir(bb, mir);
}
-MIR* ArmMir2Lir::SpecialIdentity(MIR* mir)
-{
+MIR* ArmMir2Lir::SpecialIdentity(MIR* mir) {
RegLocation rl_src;
RegLocation rl_dest;
bool wide = (mir->ssa_rep->num_uses == 2);
@@ -225,8 +216,7 @@
* Special-case code genration for simple non-throwing leaf methods.
*/
void ArmMir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir,
- SpecialCaseHandler special_case)
-{
+ SpecialCaseHandler special_case) {
current_dalvik_offset_ = mir->offset;
MIR* next_mir = NULL;
switch (special_case) {
@@ -319,8 +309,7 @@
* cbnz r_idx, lp
*/
void ArmMir2Lir::GenSparseSwitch(MIR* mir, uint32_t table_offset,
- RegLocation rl_src)
-{
+ RegLocation rl_src) {
const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
if (cu_->verbose) {
DumpSparseSwitchTable(table);
@@ -369,8 +358,7 @@
void ArmMir2Lir::GenPackedSwitch(MIR* mir, uint32_t table_offset,
- RegLocation rl_src)
-{
+ RegLocation rl_src) {
const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
if (cu_->verbose) {
DumpPackedSwitchTable(table);
@@ -427,8 +415,7 @@
*
* Total size is 4+(width * size + 1)/2 16-bit code units.
*/
-void ArmMir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src)
-{
+void ArmMir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) {
const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
// Add the table to the list - we'll process it later
FillArrayData *tab_rec =
@@ -480,8 +467,7 @@
* preserved.
*
*/
-void ArmMir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src)
-{
+void ArmMir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) {
FlushAllRegs();
DCHECK_EQ(LW_SHAPE_THIN, 0);
LoadValueDirectFixed(rl_src, r0); // Get obj
@@ -515,8 +501,7 @@
* a zero recursion count, it's safe to punch it back to the
* initial, unlock thin state with a store word.
*/
-void ArmMir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src)
-{
+void ArmMir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) {
DCHECK_EQ(LW_SHAPE_THIN, 0);
FlushAllRegs();
LoadValueDirectFixed(rl_src, r0); // Get obj
@@ -541,8 +526,7 @@
GenMemBarrier(kStoreLoad);
}
-void ArmMir2Lir::GenMoveException(RegLocation rl_dest)
-{
+void ArmMir2Lir::GenMoveException(RegLocation rl_dest) {
int ex_offset = Thread::ExceptionOffset().Int32Value();
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
int reset_reg = AllocTemp();
@@ -556,8 +540,7 @@
/*
* Mark garbage collection card. Skip if the value we're storing is null.
*/
-void ArmMir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg)
-{
+void ArmMir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg) {
int reg_card_base = AllocTemp();
int reg_card_no = AllocTemp();
LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL);
@@ -571,8 +554,7 @@
FreeTemp(reg_card_no);
}
-void ArmMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method)
-{
+void ArmMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) {
int spill_count = num_core_spills_ + num_fp_spills_;
/*
* On entry, r0, r1, r2 & r3 are live. Let the register allocation
@@ -624,8 +606,7 @@
FreeTemp(r3);
}
-void ArmMir2Lir::GenExitSequence()
-{
+void ArmMir2Lir::GenExitSequence() {
int spill_count = num_core_spills_ + num_fp_spills_;
/*
* In the exit path, r0/r1 are live - make sure they aren't
diff --git a/compiler/dex/quick/arm/fp_arm.cc b/compiler/dex/quick/arm/fp_arm.cc
index 53a5e1a..2c626a0 100644
--- a/compiler/dex/quick/arm/fp_arm.cc
+++ b/compiler/dex/quick/arm/fp_arm.cc
@@ -21,8 +21,7 @@
namespace art {
void ArmMir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
- RegLocation rl_src1, RegLocation rl_src2)
-{
+ RegLocation rl_src1, RegLocation rl_src2) {
int op = kThumbBkpt;
RegLocation rl_result;
@@ -68,8 +67,7 @@
}
void ArmMir2Lir::GenArithOpDouble(Instruction::Code opcode,
- RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
-{
+ RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
int op = kThumbBkpt;
RegLocation rl_result;
@@ -117,8 +115,7 @@
}
void ArmMir2Lir::GenConversion(Instruction::Code opcode,
- RegLocation rl_dest, RegLocation rl_src)
-{
+ RegLocation rl_dest, RegLocation rl_src) {
int op = kThumbBkpt;
int src_reg;
RegLocation rl_result;
@@ -176,8 +173,7 @@
}
void ArmMir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias,
- bool is_double)
-{
+ bool is_double) {
LIR* target = &block_label_list_[bb->taken->id];
RegLocation rl_src1;
RegLocation rl_src2;
@@ -229,8 +225,7 @@
void ArmMir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest,
- RegLocation rl_src1, RegLocation rl_src2)
-{
+ RegLocation rl_src1, RegLocation rl_src2) {
bool is_double = false;
int default_result = -1;
RegLocation rl_result;
@@ -288,8 +283,7 @@
StoreValue(rl_dest, rl_result);
}
-void ArmMir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src)
-{
+void ArmMir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src) {
RegLocation rl_result;
rl_src = LoadValue(rl_src, kFPReg);
rl_result = EvalLoc(rl_dest, kFPReg, true);
@@ -297,8 +291,7 @@
StoreValue(rl_dest, rl_result);
}
-void ArmMir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src)
-{
+void ArmMir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src) {
RegLocation rl_result;
rl_src = LoadValueWide(rl_src, kFPReg);
rl_result = EvalLoc(rl_dest, kFPReg, true);
diff --git a/compiler/dex/quick/arm/int_arm.cc b/compiler/dex/quick/arm/int_arm.cc
index feea896..ee2d76c 100644
--- a/compiler/dex/quick/arm/int_arm.cc
+++ b/compiler/dex/quick/arm/int_arm.cc
@@ -25,8 +25,7 @@
namespace art {
LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, int src1,
- int src2, LIR* target)
-{
+ int src2, LIR* target) {
OpRegReg(kOpCmp, src1, src2);
return OpCondBranch(cond, target);
}
@@ -41,8 +40,7 @@
* met, and an "E" means the instruction is executed if the condition
* is not met.
*/
-LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide)
-{
+LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) {
int mask;
int mask3 = 0;
int mask2 = 0;
@@ -86,8 +84,7 @@
* done:
*/
void ArmMir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
LIR* target1;
LIR* target2;
rl_src1 = LoadValueWide(rl_src1, kCoreReg);
@@ -121,8 +118,7 @@
}
void ArmMir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1,
- int64_t val, ConditionCode ccode)
-{
+ int64_t val, ConditionCode ccode) {
int32_t val_lo = Low32Bits(val);
int32_t val_hi = High32Bits(val);
DCHECK(ModifiedImmediate(val_lo) >= 0);
@@ -180,8 +176,7 @@
OpCmpImmBranch(ccode, low_reg, val_lo, taken);
}
-void ArmMir2Lir::GenSelect(BasicBlock* bb, MIR* mir)
-{
+void ArmMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {
RegLocation rl_result;
RegLocation rl_src = mir_graph_->GetSrc(mir, 0);
// Temporary debugging code
@@ -249,8 +244,7 @@
StoreValue(rl_dest, rl_result);
}
-void ArmMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir)
-{
+void ArmMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) {
RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0);
RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2);
// Normalize such that if either operand is constant, src2 will be constant.
@@ -315,8 +309,7 @@
* is responsible for setting branch target field.
*/
LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, int reg, int check_value,
- LIR* target)
-{
+ LIR* target) {
LIR* branch;
int mod_imm;
ArmConditionCode arm_cond = ArmConditionEncoding(cond);
@@ -341,8 +334,7 @@
return branch;
}
-LIR* ArmMir2Lir::OpRegCopyNoInsert(int r_dest, int r_src)
-{
+LIR* ArmMir2Lir::OpRegCopyNoInsert(int r_dest, int r_src) {
LIR* res;
int opcode;
if (ARM_FPREG(r_dest) || ARM_FPREG(r_src))
@@ -362,16 +354,14 @@
return res;
}
-LIR* ArmMir2Lir::OpRegCopy(int r_dest, int r_src)
-{
+LIR* ArmMir2Lir::OpRegCopy(int r_dest, int r_src) {
LIR* res = OpRegCopyNoInsert(r_dest, r_src);
AppendLIR(res);
return res;
}
void ArmMir2Lir::OpRegCopyWide(int dest_lo, int dest_hi, int src_lo,
- int src_hi)
-{
+ int src_hi) {
bool dest_fp = ARM_FPREG(dest_lo) && ARM_FPREG(dest_hi);
bool src_fp = ARM_FPREG(src_lo) && ARM_FPREG(src_hi);
DCHECK_EQ(ARM_FPREG(src_lo), ARM_FPREG(src_hi));
@@ -426,8 +416,7 @@
// Integer division by constant via reciprocal multiply (Hacker's Delight, 10-4)
bool ArmMir2Lir::SmallLiteralDivide(Instruction::Code dalvik_opcode,
- RegLocation rl_src, RegLocation rl_dest, int lit)
-{
+ RegLocation rl_src, RegLocation rl_dest, int lit) {
if ((lit < 0) || (lit >= static_cast<int>(sizeof(magic_table)/sizeof(magic_table[0])))) {
return false;
}
@@ -471,28 +460,24 @@
}
LIR* ArmMir2Lir::GenRegMemCheck(ConditionCode c_code,
- int reg1, int base, int offset, ThrowKind kind)
-{
+ int reg1, int base, int offset, ThrowKind kind) {
LOG(FATAL) << "Unexpected use of GenRegMemCheck for Arm";
return NULL;
}
RegLocation ArmMir2Lir::GenDivRemLit(RegLocation rl_dest, int reg1, int lit,
- bool is_div)
-{
+ bool is_div) {
LOG(FATAL) << "Unexpected use of GenDivRemLit for Arm";
return rl_dest;
}
RegLocation ArmMir2Lir::GenDivRem(RegLocation rl_dest, int reg1, int reg2,
- bool is_div)
-{
+ bool is_div) {
LOG(FATAL) << "Unexpected use of GenDivRem for Arm";
return rl_dest;
}
-bool ArmMir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min)
-{
+bool ArmMir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min) {
DCHECK_EQ(cu_->instruction_set, kThumb2);
RegLocation rl_src1 = info->args[0];
RegLocation rl_src2 = info->args[1];
@@ -509,13 +494,11 @@
return true;
}
-void ArmMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset)
-{
+void ArmMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) {
LOG(FATAL) << "Unexpected use of OpLea for Arm";
}
-void ArmMir2Lir::OpTlsCmp(int offset, int val)
-{
+void ArmMir2Lir::OpTlsCmp(int offset, int val) {
LOG(FATAL) << "Unexpected use of OpTlsCmp for Arm";
}
@@ -577,25 +560,21 @@
return true;
}
-LIR* ArmMir2Lir::OpPcRelLoad(int reg, LIR* target)
-{
+LIR* ArmMir2Lir::OpPcRelLoad(int reg, LIR* target) {
return RawLIR(current_dalvik_offset_, kThumb2LdrPcRel12, reg, 0, 0, 0, 0, target);
}
-LIR* ArmMir2Lir::OpVldm(int rBase, int count)
-{
+LIR* ArmMir2Lir::OpVldm(int rBase, int count) {
return NewLIR3(kThumb2Vldms, rBase, fr0, count);
}
-LIR* ArmMir2Lir::OpVstm(int rBase, int count)
-{
+LIR* ArmMir2Lir::OpVstm(int rBase, int count) {
return NewLIR3(kThumb2Vstms, rBase, fr0, count);
}
void ArmMir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src,
RegLocation rl_result, int lit,
- int first_bit, int second_bit)
-{
+ int first_bit, int second_bit) {
OpRegRegRegShift(kOpAdd, rl_result.low_reg, rl_src.low_reg, rl_src.low_reg,
EncodeShift(kArmLsl, second_bit - first_bit));
if (first_bit != 0) {
@@ -603,8 +582,7 @@
}
}
-void ArmMir2Lir::GenDivZeroCheck(int reg_lo, int reg_hi)
-{
+void ArmMir2Lir::GenDivZeroCheck(int reg_lo, int reg_hi) {
int t_reg = AllocTemp();
NewLIR4(kThumb2OrrRRRs, t_reg, reg_lo, reg_hi, 0);
FreeTemp(t_reg);
@@ -612,22 +590,19 @@
}
// Test suspend flag, return target of taken suspend branch
-LIR* ArmMir2Lir::OpTestSuspend(LIR* target)
-{
+LIR* ArmMir2Lir::OpTestSuspend(LIR* target) {
NewLIR2(kThumbSubRI8, rARM_SUSPEND, 1);
return OpCondBranch((target == NULL) ? kCondEq : kCondNe, target);
}
// Decrement register and branch on condition
-LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target)
-{
+LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) {
// Combine sub & test using sub setflags encoding here
NewLIR3(kThumb2SubsRRI12, reg, reg, 1);
return OpCondBranch(c_code, target);
}
-void ArmMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind)
-{
+void ArmMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) {
#if ANDROID_SMP != 0
int dmb_flavor;
// TODO: revisit Arm barrier kinds
@@ -646,8 +621,7 @@
#endif
}
-void ArmMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src)
-{
+void ArmMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) {
rl_src = LoadValueWide(rl_src, kCoreReg);
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
int z_reg = AllocTemp();
@@ -672,16 +646,14 @@
* is not usual for dx to generate, but it is legal (for now). In a future rev of
* dex, we'll want to make this case illegal.
*/
-bool ArmMir2Lir::BadOverlap(RegLocation rl_src, RegLocation rl_dest)
-{
+bool ArmMir2Lir::BadOverlap(RegLocation rl_src, RegLocation rl_dest) {
DCHECK(rl_src.wide);
DCHECK(rl_dest.wide);
return (abs(mir_graph_->SRegToVReg(rl_src.s_reg_low) - mir_graph_->SRegToVReg(rl_dest.s_reg_low)) == 1);
}
void ArmMir2Lir::GenMulLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
/*
* To pull off inline multiply, we have a worst-case requirement of 8 temporary
* registers. Normally for Arm, we get 5. We can get to 6 by including
@@ -754,32 +726,27 @@
}
void ArmMir2Lir::GenAddLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
LOG(FATAL) << "Unexpected use of GenAddLong for Arm";
}
void ArmMir2Lir::GenSubLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
LOG(FATAL) << "Unexpected use of GenSubLong for Arm";
}
void ArmMir2Lir::GenAndLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
LOG(FATAL) << "Unexpected use of GenAndLong for Arm";
}
void ArmMir2Lir::GenOrLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
LOG(FATAL) << "Unexpected use of GenOrLong for Arm";
}
void ArmMir2Lir::GenXorLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
LOG(FATAL) << "Unexpected use of genXoLong for Arm";
}
@@ -787,8 +754,7 @@
* Generate array load
*/
void ArmMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
- RegLocation rl_index, RegLocation rl_dest, int scale)
-{
+ RegLocation rl_index, RegLocation rl_dest, int scale) {
RegisterClass reg_class = oat_reg_class_by_size(size);
int len_offset = mirror::Array::LengthOffset().Int32Value();
int data_offset;
@@ -878,8 +844,7 @@
*
*/
void ArmMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
- RegLocation rl_index, RegLocation rl_src, int scale)
-{
+ RegLocation rl_index, RegLocation rl_src, int scale) {
RegisterClass reg_class = oat_reg_class_by_size(size);
int len_offset = mirror::Array::LengthOffset().Int32Value();
int data_offset;
@@ -968,8 +933,7 @@
*
*/
void ArmMir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array,
- RegLocation rl_index, RegLocation rl_src, int scale)
-{
+ RegLocation rl_index, RegLocation rl_src, int scale) {
int len_offset = mirror::Array::LengthOffset().Int32Value();
int data_offset = mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value();
@@ -1025,8 +989,7 @@
}
void ArmMir2Lir::GenShiftImmOpLong(Instruction::Code opcode,
- RegLocation rl_dest, RegLocation rl_src, RegLocation rl_shift)
-{
+ RegLocation rl_dest, RegLocation rl_src, RegLocation rl_shift) {
rl_src = LoadValueWide(rl_src, kCoreReg);
// Per spec, we only care about low 6 bits of shift amount.
int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f;
@@ -1099,8 +1062,7 @@
}
void ArmMir2Lir::GenArithImmOpLong(Instruction::Code opcode,
- RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
-{
+ RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
if ((opcode == Instruction::SUB_LONG_2ADDR) || (opcode == Instruction::SUB_LONG)) {
if (!rl_src2.is_const) {
// Don't bother with special handling for subtract from immediate.
diff --git a/compiler/dex/quick/arm/target_arm.cc b/compiler/dex/quick/arm/target_arm.cc
index 4bece13..7021593 100644
--- a/compiler/dex/quick/arm/target_arm.cc
+++ b/compiler/dex/quick/arm/target_arm.cc
@@ -34,26 +34,22 @@
static int fp_temps[] = {fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15};
-RegLocation ArmMir2Lir::LocCReturn()
-{
+RegLocation ArmMir2Lir::LocCReturn() {
RegLocation res = ARM_LOC_C_RETURN;
return res;
}
-RegLocation ArmMir2Lir::LocCReturnWide()
-{
+RegLocation ArmMir2Lir::LocCReturnWide() {
RegLocation res = ARM_LOC_C_RETURN_WIDE;
return res;
}
-RegLocation ArmMir2Lir::LocCReturnFloat()
-{
+RegLocation ArmMir2Lir::LocCReturnFloat() {
RegLocation res = ARM_LOC_C_RETURN_FLOAT;
return res;
}
-RegLocation ArmMir2Lir::LocCReturnDouble()
-{
+RegLocation ArmMir2Lir::LocCReturnDouble() {
RegLocation res = ARM_LOC_C_RETURN_DOUBLE;
return res;
}
@@ -85,28 +81,24 @@
// Create a double from a pair of singles.
-int ArmMir2Lir::S2d(int low_reg, int high_reg)
-{
+int ArmMir2Lir::S2d(int low_reg, int high_reg) {
return ARM_S2D(low_reg, high_reg);
}
// Return mask to strip off fp reg flags and bias.
-uint32_t ArmMir2Lir::FpRegMask()
-{
+uint32_t ArmMir2Lir::FpRegMask() {
return ARM_FP_REG_MASK;
}
// True if both regs single, both core or both double.
-bool ArmMir2Lir::SameRegType(int reg1, int reg2)
-{
+bool ArmMir2Lir::SameRegType(int reg1, int reg2) {
return (ARM_REGTYPE(reg1) == ARM_REGTYPE(reg2));
}
/*
* Decode the register id.
*/
-uint64_t ArmMir2Lir::GetRegMaskCommon(int reg)
-{
+uint64_t ArmMir2Lir::GetRegMaskCommon(int reg) {
uint64_t seed;
int shift;
int reg_id;
@@ -122,13 +114,11 @@
return (seed << shift);
}
-uint64_t ArmMir2Lir::GetPCUseDefEncoding()
-{
+uint64_t ArmMir2Lir::GetPCUseDefEncoding() {
return ENCODE_ARM_REG_PC;
}
-void ArmMir2Lir::SetupTargetResourceMasks(LIR* lir)
-{
+void ArmMir2Lir::SetupTargetResourceMasks(LIR* lir) {
DCHECK_EQ(cu_->instruction_set, kThumb2);
// Thumb2 specific setup
@@ -203,8 +193,7 @@
}
}
-ArmConditionCode ArmMir2Lir::ArmConditionEncoding(ConditionCode ccode)
-{
+ArmConditionCode ArmMir2Lir::ArmConditionEncoding(ConditionCode ccode) {
ArmConditionCode res;
switch (ccode) {
case kCondEq: res = kArmCondEq; break;
@@ -257,8 +246,7 @@
"ror"};
/* Decode and print a ARM register name */
-static char* DecodeRegList(int opcode, int vector, char* buf)
-{
+static char* DecodeRegList(int opcode, int vector, char* buf) {
int i;
bool printed = false;
buf[0] = 0;
@@ -281,8 +269,7 @@
return buf;
}
-static char* DecodeFPCSRegList(int count, int base, char* buf)
-{
+static char* DecodeFPCSRegList(int count, int base, char* buf) {
sprintf(buf, "s%d", base);
for (int i = 1; i < count; i++) {
sprintf(buf + strlen(buf), ", s%d",base + i);
@@ -290,8 +277,7 @@
return buf;
}
-static int ExpandImmediate(int value)
-{
+static int ExpandImmediate(int value) {
int mode = (value & 0xf00) >> 8;
uint32_t bits = value & 0xff;
switch (mode) {
@@ -316,8 +302,7 @@
* Interpret a format string and build a string no longer than size
* See format key in Assemble.c.
*/
-std::string ArmMir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr)
-{
+std::string ArmMir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) {
std::string buf;
int i;
const char* fmt_end = &fmt[strlen(fmt)];
@@ -455,8 +440,7 @@
return buf;
}
-void ArmMir2Lir::DumpResourceMask(LIR* arm_lir, uint64_t mask, const char* prefix)
-{
+void ArmMir2Lir::DumpResourceMask(LIR* arm_lir, uint64_t mask, const char* prefix) {
char buf[256];
buf[0] = 0;
@@ -501,8 +485,7 @@
}
}
-bool ArmMir2Lir::IsUnconditionalBranch(LIR* lir)
-{
+bool ArmMir2Lir::IsUnconditionalBranch(LIR* lir) {
return ((lir->opcode == kThumbBUncond) || (lir->opcode == kThumb2BUncond));
}
@@ -527,8 +510,7 @@
* Alloc a pair of core registers, or a double. Low reg in low byte,
* high reg in next byte.
*/
-int ArmMir2Lir::AllocTypedTempPair(bool fp_hint, int reg_class)
-{
+int ArmMir2Lir::AllocTypedTempPair(bool fp_hint, int reg_class) {
int high_reg;
int low_reg;
int res = 0;
@@ -544,15 +526,13 @@
return res;
}
-int ArmMir2Lir::AllocTypedTemp(bool fp_hint, int reg_class)
-{
+int ArmMir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) {
if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg))
return AllocTempFloat();
return AllocTemp();
}
-void ArmMir2Lir::CompilerInitializeRegAlloc()
-{
+void ArmMir2Lir::CompilerInitializeRegAlloc() {
int num_regs = sizeof(core_regs)/sizeof(*core_regs);
int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs);
int num_temps = sizeof(core_temps)/sizeof(*core_temps);
@@ -591,8 +571,7 @@
}
void ArmMir2Lir::FreeRegLocTemps(RegLocation rl_keep,
- RegLocation rl_free)
-{
+ RegLocation rl_free) {
if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) &&
(rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) {
// No overlap, free both
@@ -606,8 +585,7 @@
* machinery is in place, always spill lr.
*/
-void ArmMir2Lir::AdjustSpillMask()
-{
+void ArmMir2Lir::AdjustSpillMask() {
core_spill_mask_ |= (1 << rARM_LR);
num_core_spills_++;
}
@@ -618,8 +596,7 @@
* include any holes in the mask. Associate holes with
* Dalvik register INVALID_VREG (0xFFFFU).
*/
-void ArmMir2Lir::MarkPreservedSingle(int v_reg, int reg)
-{
+void ArmMir2Lir::MarkPreservedSingle(int v_reg, int reg) {
DCHECK_GE(reg, ARM_FP_REG_MASK + ARM_FP_CALLEE_SAVE_BASE);
reg = (reg & ARM_FP_REG_MASK) - ARM_FP_CALLEE_SAVE_BASE;
// Ensure fp_vmap_table is large enough
@@ -634,8 +611,7 @@
fp_spill_mask_ = ((1 << num_fp_spills_) - 1) << ARM_FP_CALLEE_SAVE_BASE;
}
-void ArmMir2Lir::FlushRegWide(int reg1, int reg2)
-{
+void ArmMir2Lir::FlushRegWide(int reg1, int reg2) {
RegisterInfo* info1 = GetRegInfo(reg1);
RegisterInfo* info2 = GetRegInfo(reg2);
DCHECK(info1 && info2 && info1->pair && info2->pair &&
@@ -657,8 +633,7 @@
}
}
-void ArmMir2Lir::FlushReg(int reg)
-{
+void ArmMir2Lir::FlushReg(int reg) {
RegisterInfo* info = GetRegInfo(reg);
if (info->live && info->dirty) {
info->dirty = false;
@@ -673,8 +648,7 @@
}
/* Clobber all regs that might be used by an external C call */
-void ArmMir2Lir::ClobberCalleeSave()
-{
+void ArmMir2Lir::ClobberCalleeSave() {
Clobber(r0);
Clobber(r1);
Clobber(r2);
@@ -699,8 +673,7 @@
Clobber(fr15);
}
-RegLocation ArmMir2Lir::GetReturnWideAlt()
-{
+RegLocation ArmMir2Lir::GetReturnWideAlt() {
RegLocation res = LocCReturnWide();
res.low_reg = r2;
res.high_reg = r3;
@@ -712,8 +685,7 @@
return res;
}
-RegLocation ArmMir2Lir::GetReturnAlt()
-{
+RegLocation ArmMir2Lir::GetReturnAlt() {
RegLocation res = LocCReturn();
res.low_reg = r1;
Clobber(r1);
@@ -721,15 +693,13 @@
return res;
}
-ArmMir2Lir::RegisterInfo* ArmMir2Lir::GetRegInfo(int reg)
-{
+ArmMir2Lir::RegisterInfo* ArmMir2Lir::GetRegInfo(int reg) {
return ARM_FPREG(reg) ? ®_pool_->FPRegs[reg & ARM_FP_REG_MASK]
: ®_pool_->core_regs[reg];
}
/* To be used when explicitly managing register use */
-void ArmMir2Lir::LockCallTemps()
-{
+void ArmMir2Lir::LockCallTemps() {
LockTemp(r0);
LockTemp(r1);
LockTemp(r2);
@@ -737,32 +707,27 @@
}
/* To be used when explicitly managing register use */
-void ArmMir2Lir::FreeCallTemps()
-{
+void ArmMir2Lir::FreeCallTemps() {
FreeTemp(r0);
FreeTemp(r1);
FreeTemp(r2);
FreeTemp(r3);
}
-int ArmMir2Lir::LoadHelper(int offset)
-{
+int ArmMir2Lir::LoadHelper(int offset) {
LoadWordDisp(rARM_SELF, offset, rARM_LR);
return rARM_LR;
}
-uint64_t ArmMir2Lir::GetTargetInstFlags(int opcode)
-{
+uint64_t ArmMir2Lir::GetTargetInstFlags(int opcode) {
return ArmMir2Lir::EncodingMap[opcode].flags;
}
-const char* ArmMir2Lir::GetTargetInstName(int opcode)
-{
+const char* ArmMir2Lir::GetTargetInstName(int opcode) {
return ArmMir2Lir::EncodingMap[opcode].name;
}
-const char* ArmMir2Lir::GetTargetInstFmt(int opcode)
-{
+const char* ArmMir2Lir::GetTargetInstFmt(int opcode) {
return ArmMir2Lir::EncodingMap[opcode].fmt;
}
diff --git a/compiler/dex/quick/arm/utility_arm.cc b/compiler/dex/quick/arm/utility_arm.cc
index abf921f..80f597d 100644
--- a/compiler/dex/quick/arm/utility_arm.cc
+++ b/compiler/dex/quick/arm/utility_arm.cc
@@ -22,8 +22,7 @@
/* This file contains codegen for the Thumb ISA. */
-static int EncodeImmSingle(int value)
-{
+static int EncodeImmSingle(int value) {
int res;
int bit_a = (value & 0x80000000) >> 31;
int not_bit_b = (value & 0x40000000) >> 30;
@@ -48,8 +47,7 @@
* Determine whether value can be encoded as a Thumb2 floating point
* immediate. If not, return -1. If so return encoded 8-bit value.
*/
-static int EncodeImmDouble(int64_t value)
-{
+static int EncodeImmDouble(int64_t value) {
int res;
int bit_a = (value & 0x8000000000000000ll) >> 63;
int not_bit_b = (value & 0x4000000000000000ll) >> 62;
@@ -70,8 +68,7 @@
return res;
}
-LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value)
-{
+LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value) {
DCHECK(ARM_SINGLEREG(r_dest));
if (value == 0) {
// TODO: we need better info about the target CPU. a vector exclusive or
@@ -98,8 +95,7 @@
return load_pc_rel;
}
-static int LeadingZeros(uint32_t val)
-{
+static int LeadingZeros(uint32_t val) {
uint32_t alt;
int n;
int count;
@@ -121,8 +117,7 @@
* Determine whether value can be encoded as a Thumb2 modified
* immediate. If not, return -1. If so, return i:imm3:a:bcdefgh form.
*/
-int ArmMir2Lir::ModifiedImmediate(uint32_t value)
-{
+int ArmMir2Lir::ModifiedImmediate(uint32_t value) {
int z_leading;
int z_trailing;
uint32_t b0 = value & 0xff;
@@ -151,23 +146,19 @@
return value | ((0x8 + z_leading) << 7); /* [01000..11111]:bcdefgh */
}
-bool ArmMir2Lir::InexpensiveConstantInt(int32_t value)
-{
+bool ArmMir2Lir::InexpensiveConstantInt(int32_t value) {
return (ModifiedImmediate(value) >= 0) || (ModifiedImmediate(~value) >= 0);
}
-bool ArmMir2Lir::InexpensiveConstantFloat(int32_t value)
-{
+bool ArmMir2Lir::InexpensiveConstantFloat(int32_t value) {
return EncodeImmSingle(value) >= 0;
}
-bool ArmMir2Lir::InexpensiveConstantLong(int64_t value)
-{
+bool ArmMir2Lir::InexpensiveConstantLong(int64_t value) {
return InexpensiveConstantInt(High32Bits(value)) && InexpensiveConstantInt(Low32Bits(value));
}
-bool ArmMir2Lir::InexpensiveConstantDouble(int64_t value)
-{
+bool ArmMir2Lir::InexpensiveConstantDouble(int64_t value) {
return EncodeImmDouble(value) >= 0;
}
@@ -179,8 +170,7 @@
* 1) r_dest is freshly returned from AllocTemp or
* 2) The codegen is under fixed register usage
*/
-LIR* ArmMir2Lir::LoadConstantNoClobber(int r_dest, int value)
-{
+LIR* ArmMir2Lir::LoadConstantNoClobber(int r_dest, int value) {
LIR* res;
int mod_imm;
@@ -214,23 +204,20 @@
return res;
}
-LIR* ArmMir2Lir::OpUnconditionalBranch(LIR* target)
-{
+LIR* ArmMir2Lir::OpUnconditionalBranch(LIR* target) {
LIR* res = NewLIR1(kThumbBUncond, 0 /* offset to be patched during assembly*/);
res->target = target;
return res;
}
-LIR* ArmMir2Lir::OpCondBranch(ConditionCode cc, LIR* target)
-{
+LIR* ArmMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {
LIR* branch = NewLIR2(kThumb2BCond, 0 /* offset to be patched */,
ArmConditionEncoding(cc));
branch->target = target;
return branch;
}
-LIR* ArmMir2Lir::OpReg(OpKind op, int r_dest_src)
-{
+LIR* ArmMir2Lir::OpReg(OpKind op, int r_dest_src) {
ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpBlx:
@@ -243,8 +230,7 @@
}
LIR* ArmMir2Lir::OpRegRegShift(OpKind op, int r_dest_src1, int r_src2,
- int shift)
-{
+ int shift) {
bool thumb_form = ((shift == 0) && ARM_LOWREG(r_dest_src1) && ARM_LOWREG(r_src2));
ArmOpcode opcode = kThumbBkpt;
switch (op) {
@@ -358,14 +344,12 @@
}
}
-LIR* ArmMir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2)
-{
+LIR* ArmMir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2) {
return OpRegRegShift(op, r_dest_src1, r_src2, 0);
}
LIR* ArmMir2Lir::OpRegRegRegShift(OpKind op, int r_dest, int r_src1,
- int r_src2, int shift)
-{
+ int r_src2, int shift) {
ArmOpcode opcode = kThumbBkpt;
bool thumb_form = (shift == 0) && ARM_LOWREG(r_dest) && ARM_LOWREG(r_src1) &&
ARM_LOWREG(r_src2);
@@ -430,13 +414,11 @@
}
}
-LIR* ArmMir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2)
-{
+LIR* ArmMir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2) {
return OpRegRegRegShift(op, r_dest, r_src1, r_src2, 0);
}
-LIR* ArmMir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src1, int value)
-{
+LIR* ArmMir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src1, int value) {
LIR* res;
bool neg = (value < 0);
int abs_value = (neg) ? -value : value;
@@ -560,8 +542,7 @@
}
/* Handle Thumb-only variants here - otherwise punt to OpRegRegImm */
-LIR* ArmMir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value)
-{
+LIR* ArmMir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value) {
bool neg = (value < 0);
int abs_value = (neg) ? -value : value;
bool short_form = (((abs_value & 0xff) == abs_value) && ARM_LOWREG(r_dest_src1));
@@ -605,8 +586,7 @@
}
}
-LIR* ArmMir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value)
-{
+LIR* ArmMir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) {
LIR* res = NULL;
int32_t val_lo = Low32Bits(value);
int32_t val_hi = High32Bits(value);
@@ -656,8 +636,7 @@
}
LIR* ArmMir2Lir::LoadBaseIndexed(int rBase, int r_index, int r_dest,
- int scale, OpSize size)
-{
+ int scale, OpSize size) {
bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_dest);
LIR* load;
ArmOpcode opcode = kThumbBkpt;
@@ -721,8 +700,7 @@
}
LIR* ArmMir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src,
- int scale, OpSize size)
-{
+ int scale, OpSize size) {
bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_src);
LIR* store = NULL;
ArmOpcode opcode = kThumbBkpt;
@@ -787,8 +765,7 @@
* performing null check, incoming MIR can be null.
*/
LIR* ArmMir2Lir::LoadBaseDispBody(int rBase, int displacement, int r_dest,
- int r_dest_hi, OpSize size, int s_reg)
-{
+ int r_dest_hi, OpSize size, int s_reg) {
LIR* load = NULL;
ArmOpcode opcode = kThumbBkpt;
bool short_form = false;
@@ -908,14 +885,12 @@
}
LIR* ArmMir2Lir::LoadBaseDisp(int rBase, int displacement, int r_dest,
- OpSize size, int s_reg)
-{
+ OpSize size, int s_reg) {
return LoadBaseDispBody(rBase, displacement, r_dest, -1, size, s_reg);
}
LIR* ArmMir2Lir::LoadBaseDispWide(int rBase, int displacement, int r_dest_lo,
- int r_dest_hi, int s_reg)
-{
+ int r_dest_hi, int s_reg) {
return LoadBaseDispBody(rBase, displacement, r_dest_lo, r_dest_hi, kLong, s_reg);
}
@@ -1024,19 +999,16 @@
}
LIR* ArmMir2Lir::StoreBaseDisp(int rBase, int displacement, int r_src,
- OpSize size)
-{
+ OpSize size) {
return StoreBaseDispBody(rBase, displacement, r_src, -1, size);
}
LIR* ArmMir2Lir::StoreBaseDispWide(int rBase, int displacement,
- int r_src_lo, int r_src_hi)
-{
+ int r_src_lo, int r_src_hi) {
return StoreBaseDispBody(rBase, displacement, r_src_lo, r_src_hi, kLong);
}
-LIR* ArmMir2Lir::OpFpRegCopy(int r_dest, int r_src)
-{
+LIR* ArmMir2Lir::OpFpRegCopy(int r_dest, int r_src) {
int opcode;
DCHECK_EQ(ARM_DOUBLEREG(r_dest), ARM_DOUBLEREG(r_src));
if (ARM_DOUBLEREG(r_dest)) {
@@ -1056,36 +1028,31 @@
return res;
}
-LIR* ArmMir2Lir::OpThreadMem(OpKind op, int thread_offset)
-{
+LIR* ArmMir2Lir::OpThreadMem(OpKind op, int thread_offset) {
LOG(FATAL) << "Unexpected use of OpThreadMem for Arm";
return NULL;
}
-LIR* ArmMir2Lir::OpMem(OpKind op, int rBase, int disp)
-{
+LIR* ArmMir2Lir::OpMem(OpKind op, int rBase, int disp) {
LOG(FATAL) << "Unexpected use of OpMem for Arm";
return NULL;
}
LIR* ArmMir2Lir::StoreBaseIndexedDisp(int rBase, int r_index, int scale,
int displacement, int r_src, int r_src_hi, OpSize size,
- int s_reg)
-{
+ int s_reg) {
LOG(FATAL) << "Unexpected use of StoreBaseIndexedDisp for Arm";
return NULL;
}
-LIR* ArmMir2Lir::OpRegMem(OpKind op, int r_dest, int rBase, int offset)
-{
+LIR* ArmMir2Lir::OpRegMem(OpKind op, int r_dest, int rBase, int offset) {
LOG(FATAL) << "Unexpected use of OpRegMem for Arm";
return NULL;
}
LIR* ArmMir2Lir::LoadBaseIndexedDisp(int rBase, int r_index, int scale,
int displacement, int r_dest, int r_dest_hi, OpSize size,
- int s_reg)
-{
+ int s_reg) {
LOG(FATAL) << "Unexpected use of LoadBaseIndexedDisp for Arm";
return NULL;
}