commit 217fe73a6c2f3ec44dc52c85c8a101313d048f04
author Serguei Katkov <serguei.i.katkov@intel.com> Thu Mar 27 14:41:56 2014 +0700
committer Serguei Katkov <serguei.i.katkov@intel.com> Fri Mar 28 13:12:10 2014 +0700
tree a0d856cfbfd6d94ac2f3290491a24545838e31e6
parent ad174d1b54bf2fa477bec71a0ca93595f54b8fe9

Annotate Dalvik VR access as both use and def if we use it in this way

Some 2addr operations use direct access to VR in memory as both def and use but
annotate its only as def. It results in later optimizations like reorder
of LIRs can re-order this operation with other mov.

Change-Id: I04ac40c9f229af6f1e5c5f91f4901b1452509582
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>

compiler/dex/quick/x86/int_x86.cc

diff --git a/compiler/dex/quick/x86/int_x86.cc b/compiler/dex/quick/x86/int_x86.cc
index 37b2b37..851f448 100644
--- a/compiler/dex/quick/x86/int_x86.cc
+++ b/compiler/dex/quick/x86/int_x86.cc
@@ -1179,10 +1179,14 @@
 
   LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, rl_src.reg.GetLowReg());
   AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2,
+                          true /* is_load */, true /* is64bit */);
+  AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2,
                           false /* is_load */, true /* is64bit */);
   x86op = GetOpcode(op, rl_dest, rl_src, true);
   lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, rl_src.reg.GetHighReg());
   AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2,
+                          true /* is_load */, true /* is64bit */);
+  AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2,
                           false /* is_load */, true /* is64bit */);
   FreeTemp(rl_src.reg);
 }
@@ -1679,12 +1683,16 @@
       X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo);
       LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val_lo);
       AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2,
+                              true /* is_load */, true /* is64bit */);
+      AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2,
                               false /* is_load */, true /* is64bit */);
     }
     if (!IsNoOp(op, val_hi)) {
       X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi);
       LIR *lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, val_hi);
       AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2,
+                                true /* is_load */, true /* is64bit */);
+      AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2,
                                 false /* is_load */, true /* is64bit */);
     }
     return;