riscv64: store double result in two vreg slots

Test: Run these opcodes against all interpreter
tests on a Linux RISC-V VM.

(1) setup
  lunch aosp_riscv64-userdebug

  export ART_TEST_SSH_USER=ubuntu
  export ART_TEST_SSH_HOST=localhost
  export ART_TEST_SSH_PORT=10001
  export ART_TEST_ON_VM=true

  . art/tools/buildbot-utils.sh
  art/tools/buildbot-build.sh --target

  # Create, boot and configure the VM.
  art/tools/buildbot-vm.sh create
  art/tools/buildbot-vm.sh boot
  art/tools/buildbot-vm.sh setup-ssh  # password: 'ubuntu'

  art/tools/buildbot-cleanup-device.sh
  art/tools/buildbot-setup-device.sh
  art/tools/buildbot-sync.sh

(2) test
  art/test.py --target -r --no-prebuild --ndebug --64  -j 12 --cdex-none --interpreter

Clean with `m check_cfi` too.
Also exercised on cuttlefish boot. No SIGSEGV or SIGILL noted.

Bug: 283082047

Change-Id: I6317bd21236c569e32aba7bd300ecc78d1831e3b
diff --git a/runtime/interpreter/mterp/riscv64/floating_point.S b/runtime/interpreter/mterp/riscv64/floating_point.S
index ba64624..dff9e5a 100644
--- a/runtime/interpreter/mterp/riscv64/floating_point.S
+++ b/runtime/interpreter/mterp/riscv64/floating_point.S
@@ -334,5 +334,6 @@
     $instr                   // read fa0 and f1, write result to fa0.
                              // instr may be a function call.
     GET_INST_OPCODE t1       // t1 holds next opcode
-    SET_VREG_FLOAT fa0, s11  // fp[A] := fa0
+    SET_VREG_FLOAT fa0, s11, is_double=$is_double
+                             // fp[A] := fa0
     GOTO_OPCODE t1           // continue to next