commit 1ba0f596e9e4ddd778ab431237d11baa85594eba
author Nicolas Geoffray <ngeoffray@google.com> Mon Oct 27 15:14:55 2014 +0000
committer Nicolas Geoffray <ngeoffray@google.com> Mon Oct 27 17:20:35 2014 +0000
tree c1d51616adf4d98aab3ebccf47ad5146635cb87f
parent 1ef3495abfa2a858b3cc7a1844383c8e7dff0b60

Support hard float on arm in optimizing compiler.

Also bump oat version, needed after latest hard float switch.

Change-Id: Idf5acfb36c07e74acff00edab998419a3c6b2965

compiler/optimizing/code_generator.cc

diff --git a/compiler/optimizing/code_generator.cc b/compiler/optimizing/code_generator.cc
index c4286a4..28ff1cf 100644
--- a/compiler/optimizing/code_generator.cc
+++ b/compiler/optimizing/code_generator.cc
@@ -111,6 +111,20 @@
     }
   }
   LOG(FATAL) << "Could not find a register in baseline register allocator";
+  UNREACHABLE();
+  return -1;
+}
+
+size_t CodeGenerator::FindTwoFreeConsecutiveEntries(bool* array, size_t length) {
+  for (size_t i = 0; i < length - 1; ++i) {
+    if (!array[i] && !array[i + 1]) {
+      array[i] = true;
+      array[i + 1] = true;
+      return i;
+    }
+  }
+  LOG(FATAL) << "Could not find a register in baseline register allocator";
+  UNREACHABLE();
   return -1;
 }
 
@@ -180,6 +194,11 @@
     } else if (loc.IsFpuRegister()) {
       DCHECK(!blocked_fpu_registers_[loc.reg()]);
       blocked_fpu_registers_[loc.reg()] = true;
+    } else if (loc.IsFpuRegisterPair()) {
+      DCHECK(!blocked_fpu_registers_[loc.AsFpuRegisterPairLow<int>()]);
+      blocked_fpu_registers_[loc.AsFpuRegisterPairLow<int>()] = true;
+      DCHECK(!blocked_fpu_registers_[loc.AsFpuRegisterPairHigh<int>()]);
+      blocked_fpu_registers_[loc.AsFpuRegisterPairHigh<int>()] = true;
     } else if (loc.IsRegisterPair()) {
       DCHECK(!blocked_core_registers_[loc.AsRegisterPairLow<int>()]);
       blocked_core_registers_[loc.AsRegisterPairLow<int>()] = true;