RFC: ARM64: Split arm64 codegen into scalar and vector (SVE and NEON).
This is a first CL in the series of introducing arm64 SVE support
in ART. The patch splits the codegen functionality into scalar and
vector ones and for the latter introduces NEON and SVE
implementations. SVE one currently is an exact copy of NEON one -
for the sake of testing and an easy diff when the next CL comes
with an actual SVE instructions support.
The patch effectively doesn't change any behavior; NEON mode is
used for vector instructions, tests pass.
Test: test-art-target.
Change-Id: I5f7f2c8218330998e5a733a56f42473526cd58e6
diff --git a/compiler/optimizing/code_generator.h b/compiler/optimizing/code_generator.h
index 84bf491..ff2be47 100644
--- a/compiler/optimizing/code_generator.h
+++ b/compiler/optimizing/code_generator.h
@@ -223,6 +223,9 @@
virtual const Assembler& GetAssembler() const = 0;
virtual size_t GetWordSize() const = 0;
+ // Returns whether the target supports predicated SIMD instructions.
+ virtual bool SupportsPredicatedSIMD() const { return false; }
+
// Get FP register width in bytes for spilling/restoring in the slow paths.
//
// Note: In SIMD graphs this should return SIMD register width as all FP and SIMD registers