Quick: PC-relative loads from dex cache arrays on x86.
Rewrite all PC-relative addressing on x86 and implement
PC-relative loads from dex cache arrays. Don't adjust the
base to point to the start of the method, let it point to
the anchor, i.e. the target of the "call +0" insn.
Change-Id: Ic22544a8bc0c5e49eb00a75154dc8f3ead816989
diff --git a/compiler/dex/quick/arm/utility_arm.cc b/compiler/dex/quick/arm/utility_arm.cc
index c3371cf..25ea694 100644
--- a/compiler/dex/quick/arm/utility_arm.cc
+++ b/compiler/dex/quick/arm/utility_arm.cc
@@ -1273,13 +1273,14 @@
if (pc_rel_temp_ != nullptr) {
// Now, if the dex cache array base temp is used only once outside any loops (weight = 1),
- // avoid the promotion, otherwise boost the weight by factor 4 because the full PC-relative
- // load sequence is 4 instructions long.
+ // avoid the promotion, otherwise boost the weight by factor 3 because the full PC-relative
+ // load sequence is 4 instructions long and by promoting the PC base we save up to 3
+ // instructions per use.
int p_map_idx = SRegToPMap(pc_rel_temp_->s_reg_low);
if (core_counts[p_map_idx].count == 1) {
core_counts[p_map_idx].count = 0;
} else {
- core_counts[p_map_idx].count *= 4;
+ core_counts[p_map_idx].count *= 3;
}
}
}