Optimizing: Improve shift simplification, x >>> 64.
Simplify shifts by a multiple of bit size, not just 0.
ARM codegen does not expect to see such shifts and it
is guarding against them with a DCHECK().
Bug: 27638111
Change-Id: I3ae8383d7edefa0facd375ce511e7a226d5468a1
diff --git a/compiler/optimizing/instruction_simplifier.cc b/compiler/optimizing/instruction_simplifier.cc
index 09f841c..f1f4652 100644
--- a/compiler/optimizing/instruction_simplifier.cc
+++ b/compiler/optimizing/instruction_simplifier.cc
@@ -235,7 +235,10 @@
HInstruction* input_other = instruction->GetLeastConstantLeft();
if (input_cst != nullptr) {
- if (input_cst->IsZero()) {
+ int64_t cst = Int64FromConstant(input_cst);
+ int64_t mask =
+ (input_cst->GetType() == Primitive::kPrimLong) ? kMaxLongShiftValue : kMaxIntShiftValue;
+ if ((cst & mask) == 0) {
// Replace code looking like
// SHL dst, src, 0
// with