commit 14d90579f013b374638b599361970557ed4b3f09
author Roland Levillain <rpl@google.com> Thu Jul 16 10:52:26 2015 +0100
committer Roland Levillain <rpl@google.com> Thu Jul 16 10:52:26 2015 +0100
tree fe8f9f7b527e73c20078557eefd74615c2cfc7f8
parent 5c03f3698f5e2e0d762e2e15ec00310b6cdab4fe

Use (D)CHECK_ALIGNED more.

Change-Id: I9d740f6a88d01e028d4ddc3e4e62b0a73ea050af

compiler/dex/quick/arm/utility_arm.cc

diff --git a/compiler/dex/quick/arm/utility_arm.cc b/compiler/dex/quick/arm/utility_arm.cc
index 2ef92f8..062f7af 100644
--- a/compiler/dex/quick/arm/utility_arm.cc
+++ b/compiler/dex/quick/arm/utility_arm.cc
@@ -880,7 +880,7 @@
 LIR* ArmMir2Lir::LoadStoreUsingInsnWithOffsetImm8Shl2(ArmOpcode opcode, RegStorage r_base,
                                                       int displacement, RegStorage r_src_dest,
                                                       RegStorage r_work) {
-  DCHECK_EQ(displacement & 3, 0);
+  DCHECK_ALIGNED(displacement, 4);
   constexpr int kOffsetMask = 0xff << 2;
   int encoded_disp = (displacement & kOffsetMask) >> 2;  // Within range of the instruction.
   RegStorage r_ptr = r_base;
@@ -942,7 +942,7 @@
         already_generated = true;
         break;
       }
-      DCHECK_EQ((displacement & 0x3), 0);
+      DCHECK_ALIGNED(displacement, 4);
       scale = 2;
       if (r_dest.Low8() && (r_base == rs_rARM_PC) && (displacement <= 1020) &&
           (displacement >= 0)) {
@@ -959,14 +959,14 @@
       }
       break;
     case kUnsignedHalf:
-      DCHECK_EQ((displacement & 0x1), 0);
+      DCHECK_ALIGNED(displacement, 2);
       scale = 1;
       short_form = all_low && (displacement >> (5 + scale)) == 0;
       opcode16 = kThumbLdrhRRI5;
       opcode32 = kThumb2LdrhRRI12;
       break;
     case kSignedHalf:
-      DCHECK_EQ((displacement & 0x1), 0);
+      DCHECK_ALIGNED(displacement, 2);
       scale = 1;
       DCHECK_EQ(opcode16, kThumbBkpt);  // Not available.
       opcode32 = kThumb2LdrshRRI12;
@@ -1096,7 +1096,7 @@
         already_generated = true;
         break;
       }
-      DCHECK_EQ((displacement & 0x3), 0);
+      DCHECK_ALIGNED(displacement, 4);
       scale = 2;
       if (r_src.Low8() && (r_base == rs_r13sp) && (displacement <= 1020) && (displacement >= 0)) {
         short_form = true;
@@ -1109,7 +1109,7 @@
       break;
     case kUnsignedHalf:
     case kSignedHalf:
-      DCHECK_EQ((displacement & 0x1), 0);
+      DCHECK_ALIGNED(displacement, 2);
       scale = 1;
       short_form = all_low && (displacement >> (5 + scale)) == 0;
       opcode16 = kThumbStrhRRI5;