diff --git a/compiler/optimizing/code_generator_arm64.cc b/compiler/optimizing/code_generator_arm64.cc
index 8a8530f..edc8321 100644
--- a/compiler/optimizing/code_generator_arm64.cc
+++ b/compiler/optimizing/code_generator_arm64.cc
@@ -3061,7 +3061,7 @@
   Register dividend = InputRegisterAt(instruction, 0);
 
   Register final_dividend;
-  if (HasNonNegativeResultOrMinInt(instruction->GetLeft())) {
+  if (HasNonNegativeOrMinIntInputAt(instruction, 0)) {
     // No need to adjust the result for non-negative dividends or the INT32_MIN/INT64_MIN dividends.
     // NOTE: The generated code for HDiv correctly works for the INT32_MIN/INT64_MIN dividends:
     //   imm == 2
@@ -3107,12 +3107,14 @@
   }
 }
 
-// Return true if the magic number was modified by subtracting 2^32. So dividend needs to be added.
+// Return true if the magic number was modified by subtracting 2^32(Int32 div) or 2^64(Int64 div).
+// So dividend needs to be added.
 static inline bool NeedToAddDividend(int64_t magic_number, int64_t divisor) {
   return divisor > 0 && magic_number < 0;
 }
 
-// Return true if the magic number was modified by adding 2^32. So dividend needs to be subtracted.
+// Return true if the magic number was modified by adding 2^32(Int32 div) or 2^64(Int64 div).
+// So dividend needs to be subtracted.
 static inline bool NeedToSubDividend(int64_t magic_number, int64_t divisor) {
   return divisor < 0 && magic_number > 0;
 }
@@ -3177,7 +3179,8 @@
   // This allows to use CINC MI which has latency 1.
   bool use_cond_inc = false;
 
-  // As magic_number can be modified to fit into 32 bits, check whether the correction is needed.
+  // Some combinations of magic_number and the divisor require to correct the result.
+  // Check whether the correction is needed.
   if (NeedToAddDividend(magic, imm)) {
     __ Adds(temp, temp, dividend);
     use_cond_inc = true;
@@ -3242,7 +3245,7 @@
 
   // Extract the result from the high 32 bits and apply the final right shift.
   DCHECK_LT(shift, 32);
-  if (imm > 0 && IsGEZero(instruction->GetLeft())) {
+  if (imm > 0 && HasNonNegativeInputAt(instruction, 0)) {
     // No need to adjust the result for a non-negative dividend and a positive divisor.
     if (instruction->IsDiv()) {
       __ Lsr(out.X(), temp.X(), 32 + shift);
@@ -5633,7 +5636,7 @@
   Register out = OutputRegister(instruction);
   Register dividend = InputRegisterAt(instruction, 0);
 
-  if (HasNonNegativeResultOrMinInt(instruction->GetLeft())) {
+  if (HasNonNegativeOrMinIntInputAt(instruction, 0)) {
     // No need to adjust the result for non-negative dividends or the INT32_MIN/INT64_MIN dividends.
     // NOTE: The generated code for HRem correctly works for the INT32_MIN/INT64_MIN dividends.
     // INT*_MIN % imm must be 0 for any imm of power 2. 'and' works only with bits