Fix cpplint whitespace/blank_line issues
Change-Id: Ice937e95e23dd622c17054551d4ae4cebd0ef8a2
diff --git a/compiler/dex/quick/arm/assemble_arm.cc b/compiler/dex/quick/arm/assemble_arm.cc
index f4aa1f3..0649c9f 100644
--- a/compiler/dex/quick/arm/assemble_arm.cc
+++ b/compiler/dex/quick/arm/assemble_arm.cc
@@ -1007,7 +1007,6 @@
AssemblerStatus res = kSuccess; // Assume success
for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {
-
if (lir->opcode < 0) {
/* 1 means padding is needed */
if ((lir->opcode == kPseudoPseudoAlign4) && (lir->operands[0] == 1)) {
diff --git a/compiler/dex/quick/codegen_util.cc b/compiler/dex/quick/codegen_util.cc
index e169dc8..8698b1f 100644
--- a/compiler/dex/quick/codegen_util.cc
+++ b/compiler/dex/quick/codegen_util.cc
@@ -969,7 +969,6 @@
/* Method is not empty */
if (first_lir_insn_) {
-
// mark the targets of switch statement case labels
ProcessSwitchTables();
@@ -979,9 +978,7 @@
if (cu_->verbose) {
CodegenDump();
}
-
}
-
}
CompiledMethod* Mir2Lir::GetCompiledMethod() {
diff --git a/compiler/dex/quick/gen_invoke.cc b/compiler/dex/quick/gen_invoke.cc
index 14e395c..fd8f86b 100644
--- a/compiler/dex/quick/gen_invoke.cc
+++ b/compiler/dex/quick/gen_invoke.cc
@@ -736,7 +736,6 @@
const MethodReference& target_method,
uint32_t vtable_idx, uintptr_t direct_code, uintptr_t direct_method,
InvokeType type, bool skip_this) {
-
// If we can treat it as non-range (Jumbo ops will use range form)
if (info->num_arg_words <= 5)
return GenDalvikArgsNoRange(info, call_state, pcrLabel,
diff --git a/compiler/dex/quick/local_optimizations.cc b/compiler/dex/quick/local_optimizations.cc
index eb27bf8..2e9c845 100644
--- a/compiler/dex/quick/local_optimizations.cc
+++ b/compiler/dex/quick/local_optimizations.cc
@@ -73,11 +73,14 @@
void Mir2Lir::ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir) {
LIR* this_lir;
- if (head_lir == tail_lir) return;
+ if (head_lir == tail_lir) {
+ return;
+ }
for (this_lir = PREV_LIR(tail_lir); this_lir != head_lir; this_lir = PREV_LIR(this_lir)) {
-
- if (is_pseudo_opcode(this_lir->opcode)) continue;
+ if (is_pseudo_opcode(this_lir->opcode)) {
+ continue;
+ }
int sink_distance = 0;
@@ -110,7 +113,9 @@
* Currently only eliminate redundant ld/st for constant and Dalvik
* register accesses.
*/
- if (!(this_mem_mask & (ENCODE_LITERAL | ENCODE_DALVIK_REG))) continue;
+ if (!(this_mem_mask & (ENCODE_LITERAL | ENCODE_DALVIK_REG))) {
+ continue;
+ }
uint64_t stop_def_reg_mask = this_lir->def_mask & ~ENCODE_MEM;
uint64_t stop_use_reg_mask;
@@ -127,12 +132,13 @@
}
for (check_lir = NEXT_LIR(this_lir); check_lir != tail_lir; check_lir = NEXT_LIR(check_lir)) {
-
/*
* Skip already dead instructions (whose dataflow information is
* outdated and misleading).
*/
- if (check_lir->flags.is_nop || is_pseudo_opcode(check_lir->opcode)) continue;
+ if (check_lir->flags.is_nop || is_pseudo_opcode(check_lir->opcode)) {
+ continue;
+ }
uint64_t check_mem_mask = (check_lir->use_mask | check_lir->def_mask) & ENCODE_MEM;
uint64_t alias_condition = this_mem_mask & check_mem_mask;
@@ -274,12 +280,15 @@
LIR* prev_inst_list[MAX_HOIST_DISTANCE];
/* Empty block */
- if (head_lir == tail_lir) return;
+ if (head_lir == tail_lir) {
+ return;
+ }
/* Start from the second instruction */
for (this_lir = NEXT_LIR(head_lir); this_lir != tail_lir; this_lir = NEXT_LIR(this_lir)) {
-
- if (is_pseudo_opcode(this_lir->opcode)) continue;
+ if (is_pseudo_opcode(this_lir->opcode)) {
+ continue;
+ }
uint64_t target_flags = GetTargetInstFlags(this_lir->opcode);
/* Skip non-interesting instructions */
@@ -312,12 +321,13 @@
/* Try to hoist the load to a good spot */
for (check_lir = PREV_LIR(this_lir); check_lir != head_lir; check_lir = PREV_LIR(check_lir)) {
-
/*
* Skip already dead instructions (whose dataflow information is
* outdated and misleading).
*/
- if (check_lir->flags.is_nop) continue;
+ if (check_lir->flags.is_nop) {
+ continue;
+ }
uint64_t check_mem_mask = check_lir->def_mask & ENCODE_MEM;
uint64_t alias_condition = stop_use_all_mask & check_mem_mask;
@@ -355,7 +365,9 @@
*/
if (stop_here || !is_pseudo_opcode(check_lir->opcode)) {
prev_inst_list[next_slot++] = check_lir;
- if (next_slot == MAX_HOIST_DISTANCE) break;
+ if (next_slot == MAX_HOIST_DISTANCE) {
+ break;
+ }
}
/* Found a new place to put the load - move it here */
@@ -400,12 +412,16 @@
* If the first instruction is a load, don't hoist anything
* above it since it is unlikely to be beneficial.
*/
- if (GetTargetInstFlags(cur_lir->opcode) & IS_LOAD) continue;
+ if (GetTargetInstFlags(cur_lir->opcode) & IS_LOAD) {
+ continue;
+ }
/*
* If the remaining number of slots is less than LD_LATENCY,
* insert the hoisted load here.
*/
- if (slot < LD_LATENCY) break;
+ if (slot < LD_LATENCY) {
+ break;
+ }
}
// Don't look across a barrier label
@@ -461,7 +477,6 @@
LIR* this_lir;
for (this_lir = first_lir_insn_; this_lir != last_lir_insn_; this_lir = NEXT_LIR(this_lir)) {
-
/* Branch to the next instruction */
if (IsUnconditionalBranch(this_lir)) {
LIR* next_lir = this_lir;
diff --git a/compiler/dex/quick/mips/codegen_mips.h b/compiler/dex/quick/mips/codegen_mips.h
index 376ad7f..802ff62 100644
--- a/compiler/dex/quick/mips/codegen_mips.h
+++ b/compiler/dex/quick/mips/codegen_mips.h
@@ -24,7 +24,6 @@
class MipsMir2Lir : public Mir2Lir {
public:
-
MipsMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
// Required for target - codegen utilities.
@@ -175,7 +174,6 @@
private:
void ConvertShortToLongBranch(LIR* lir);
-
};
} // namespace art
diff --git a/compiler/dex/quick/mir_to_lir.h b/compiler/dex/quick/mir_to_lir.h
index abb687c..41e5a2d 100644
--- a/compiler/dex/quick/mir_to_lir.h
+++ b/compiler/dex/quick/mir_to_lir.h
@@ -166,7 +166,6 @@
#define is_pseudo_opcode(opcode) (static_cast<int>(opcode) < 0)
class Mir2Lir : public Backend {
-
public:
struct SwitchTable {
int offset;
diff --git a/compiler/dex/quick/x86/codegen_x86.h b/compiler/dex/quick/x86/codegen_x86.h
index 4fa9dfb..edb5ae5 100644
--- a/compiler/dex/quick/x86/codegen_x86.h
+++ b/compiler/dex/quick/x86/codegen_x86.h
@@ -24,7 +24,6 @@
class X86Mir2Lir : public Mir2Lir {
public:
-
X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
// Required for target - codegen helpers.