MIPS: Remove mterp reliance on code item layout
This is a follow-up to
https://android-review.googlesource.com/529455
Test: ./run-test --interpreter 003-omnibus-opcodes
Test: ./run-test --interpreter 083-compiler-regressions
Test: ./run-test --interpreter --64 003-omnibus-opcodes
Test: ./run-test --interpreter --64 083-compiler-regressions
Change-Id: I72a3f6b0c3583a149db7aa151a79358fe15223b5
diff --git a/runtime/interpreter/mterp/mips/entry.S b/runtime/interpreter/mterp/mips/entry.S
index f617a4d..03de985 100644
--- a/runtime/interpreter/mterp/mips/entry.S
+++ b/runtime/interpreter/mterp/mips/entry.S
@@ -25,7 +25,7 @@
/*
* On entry:
* a0 Thread* self
- * a1 code_item
+ * a1 dex_instructions
* a2 ShadowFrame
* a3 JValue* result_register
*
@@ -43,8 +43,8 @@
/* Remember the return register */
sw a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2)
- /* Remember the code_item */
- sw a1, SHADOWFRAME_CODE_ITEM_OFFSET(a2)
+ /* Remember the dex instruction pointer */
+ sw a1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(a2)
/* set up "named" registers */
move rSELF, a0
@@ -52,8 +52,7 @@
addu rFP, a2, SHADOWFRAME_VREGS_OFFSET # point to vregs.
EAS2(rREFS, rFP, a0) # point to reference array in shadow frame
lw a0, SHADOWFRAME_DEX_PC_OFFSET(a2) # Get starting dex_pc
- addu rPC, a1, CODEITEM_INSNS_OFFSET # Point to base of insns[]
- EAS1(rPC, rPC, a0) # Create direct pointer to 1st dex opcode
+ EAS1(rPC, a1, a0) # Create direct pointer to 1st dex opcode
EXPORT_PC()
diff --git a/runtime/interpreter/mterp/mips/footer.S b/runtime/interpreter/mterp/mips/footer.S
index 9909dfe..6e1ba1c 100644
--- a/runtime/interpreter/mterp/mips/footer.S
+++ b/runtime/interpreter/mterp/mips/footer.S
@@ -95,12 +95,10 @@
addu a1, rFP, OFF_FP_SHADOWFRAME
JAL(MterpHandleException) # (self, shadow_frame)
beqz v0, MterpExceptionReturn # no local catch, back to caller.
- lw a0, OFF_FP_CODE_ITEM(rFP)
+ lw a0, OFF_FP_DEX_INSTRUCTIONS(rFP)
lw a1, OFF_FP_DEX_PC(rFP)
lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF)
- addu rPC, a0, CODEITEM_INSNS_OFFSET
- sll a1, a1, 1
- addu rPC, rPC, a1 # generate new dex_pc_ptr
+ EAS1(rPC, a0, a1) # generate new dex_pc_ptr
/* Do we need to switch interpreters? */
JAL(MterpShouldSwitchInterpreters)
bnez v0, MterpFallback
diff --git a/runtime/interpreter/mterp/mips/header.S b/runtime/interpreter/mterp/mips/header.S
index 0ce7745..e4552dd 100644
--- a/runtime/interpreter/mterp/mips/header.S
+++ b/runtime/interpreter/mterp/mips/header.S
@@ -216,7 +216,7 @@
#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET)
#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET)
#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET)
-#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET)
+#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET)
#define OFF_FP_SHADOWFRAME OFF_FP(0)
#define MTERP_PROFILE_BRANCHES 1
@@ -238,9 +238,8 @@
sw rPC, OFF_FP_DEX_PC_PTR(rFP)
#define EXPORT_DEX_PC(tmp) \
- lw tmp, OFF_FP_CODE_ITEM(rFP); \
+ lw tmp, OFF_FP_DEX_INSTRUCTIONS(rFP); \
sw rPC, OFF_FP_DEX_PC_PTR(rFP); \
- addu tmp, CODEITEM_INSNS_OFFSET; \
subu tmp, rPC, tmp; \
sra tmp, tmp, 1; \
sw tmp, OFF_FP_DEX_PC(rFP)
diff --git a/runtime/interpreter/mterp/mips64/entry.S b/runtime/interpreter/mterp/mips64/entry.S
index 5536966..436b88d 100644
--- a/runtime/interpreter/mterp/mips64/entry.S
+++ b/runtime/interpreter/mterp/mips64/entry.S
@@ -27,7 +27,7 @@
/*
* On entry:
* a0 Thread* self
- * a1 code_item
+ * a1 dex_instructions
* a2 ShadowFrame
* a3 JValue* result_register
*
@@ -63,17 +63,16 @@
/* Remember the return register */
sd a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2)
- /* Remember the code_item */
- sd a1, SHADOWFRAME_CODE_ITEM_OFFSET(a2)
+ /* Remember the dex instruction pointer */
+ sd a1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(a2)
/* set up "named" registers */
move rSELF, a0
daddu rFP, a2, SHADOWFRAME_VREGS_OFFSET
lw v0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2)
dlsa rREFS, v0, rFP, 2
- daddu rPC, a1, CODEITEM_INSNS_OFFSET
lw v0, SHADOWFRAME_DEX_PC_OFFSET(a2)
- dlsa rPC, v0, rPC, 1
+ dlsa rPC, v0, a1, 1
EXPORT_PC
/* Starting ibase */
diff --git a/runtime/interpreter/mterp/mips64/footer.S b/runtime/interpreter/mterp/mips64/footer.S
index 312fa9c..779b1fb 100644
--- a/runtime/interpreter/mterp/mips64/footer.S
+++ b/runtime/interpreter/mterp/mips64/footer.S
@@ -55,11 +55,10 @@
daddu a1, rFP, OFF_FP_SHADOWFRAME
jal MterpHandleException # (self, shadow_frame)
beqzc v0, MterpExceptionReturn # no local catch, back to caller.
- ld a0, OFF_FP_CODE_ITEM(rFP)
+ ld a0, OFF_FP_DEX_INSTRUCTIONS(rFP)
lwu a1, OFF_FP_DEX_PC(rFP)
REFRESH_IBASE
- daddu rPC, a0, CODEITEM_INSNS_OFFSET
- dlsa rPC, a1, rPC, 1 # generate new dex_pc_ptr
+ dlsa rPC, a1, a0, 1 # generate new dex_pc_ptr
/* Do we need to switch interpreters? */
jal MterpShouldSwitchInterpreters
bnezc v0, MterpFallback
diff --git a/runtime/interpreter/mterp/mips64/header.S b/runtime/interpreter/mterp/mips64/header.S
index 264c411..d1acefd 100644
--- a/runtime/interpreter/mterp/mips64/header.S
+++ b/runtime/interpreter/mterp/mips64/header.S
@@ -114,7 +114,7 @@
#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET)
#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET)
#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET)
-#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET)
+#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET)
#define OFF_FP_SHADOWFRAME OFF_FP(0)
#define MTERP_PROFILE_BRANCHES 1
diff --git a/runtime/interpreter/mterp/out/mterp_mips.S b/runtime/interpreter/mterp/out/mterp_mips.S
index e830835..8cc1b19 100644
--- a/runtime/interpreter/mterp/out/mterp_mips.S
+++ b/runtime/interpreter/mterp/out/mterp_mips.S
@@ -223,7 +223,7 @@
#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET)
#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET)
#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET)
-#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET)
+#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET)
#define OFF_FP_SHADOWFRAME OFF_FP(0)
#define MTERP_PROFILE_BRANCHES 1
@@ -245,9 +245,8 @@
sw rPC, OFF_FP_DEX_PC_PTR(rFP)
#define EXPORT_DEX_PC(tmp) \
- lw tmp, OFF_FP_CODE_ITEM(rFP); \
+ lw tmp, OFF_FP_DEX_INSTRUCTIONS(rFP); \
sw rPC, OFF_FP_DEX_PC_PTR(rFP); \
- addu tmp, CODEITEM_INSNS_OFFSET; \
subu tmp, rPC, tmp; \
sra tmp, tmp, 1; \
sw tmp, OFF_FP_DEX_PC(rFP)
@@ -759,7 +758,7 @@
/*
* On entry:
* a0 Thread* self
- * a1 code_item
+ * a1 dex_instructions
* a2 ShadowFrame
* a3 JValue* result_register
*
@@ -777,8 +776,8 @@
/* Remember the return register */
sw a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2)
- /* Remember the code_item */
- sw a1, SHADOWFRAME_CODE_ITEM_OFFSET(a2)
+ /* Remember the dex instruction pointer */
+ sw a1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(a2)
/* set up "named" registers */
move rSELF, a0
@@ -786,8 +785,7 @@
addu rFP, a2, SHADOWFRAME_VREGS_OFFSET # point to vregs.
EAS2(rREFS, rFP, a0) # point to reference array in shadow frame
lw a0, SHADOWFRAME_DEX_PC_OFFSET(a2) # Get starting dex_pc
- addu rPC, a1, CODEITEM_INSNS_OFFSET # Point to base of insns[]
- EAS1(rPC, rPC, a0) # Create direct pointer to 1st dex opcode
+ EAS1(rPC, a1, a0) # Create direct pointer to 1st dex opcode
EXPORT_PC()
@@ -12655,12 +12653,10 @@
addu a1, rFP, OFF_FP_SHADOWFRAME
JAL(MterpHandleException) # (self, shadow_frame)
beqz v0, MterpExceptionReturn # no local catch, back to caller.
- lw a0, OFF_FP_CODE_ITEM(rFP)
+ lw a0, OFF_FP_DEX_INSTRUCTIONS(rFP)
lw a1, OFF_FP_DEX_PC(rFP)
lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF)
- addu rPC, a0, CODEITEM_INSNS_OFFSET
- sll a1, a1, 1
- addu rPC, rPC, a1 # generate new dex_pc_ptr
+ EAS1(rPC, a0, a1) # generate new dex_pc_ptr
/* Do we need to switch interpreters? */
JAL(MterpShouldSwitchInterpreters)
bnez v0, MterpFallback
diff --git a/runtime/interpreter/mterp/out/mterp_mips64.S b/runtime/interpreter/mterp/out/mterp_mips64.S
index b6af040..139ee25 100644
--- a/runtime/interpreter/mterp/out/mterp_mips64.S
+++ b/runtime/interpreter/mterp/out/mterp_mips64.S
@@ -121,7 +121,7 @@
#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET)
#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET)
#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET)
-#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET)
+#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET)
#define OFF_FP_SHADOWFRAME OFF_FP(0)
#define MTERP_PROFILE_BRANCHES 1
@@ -361,7 +361,7 @@
/*
* On entry:
* a0 Thread* self
- * a1 code_item
+ * a1 dex_instructions
* a2 ShadowFrame
* a3 JValue* result_register
*
@@ -397,17 +397,16 @@
/* Remember the return register */
sd a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2)
- /* Remember the code_item */
- sd a1, SHADOWFRAME_CODE_ITEM_OFFSET(a2)
+ /* Remember the dex instruction pointer */
+ sd a1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(a2)
/* set up "named" registers */
move rSELF, a0
daddu rFP, a2, SHADOWFRAME_VREGS_OFFSET
lw v0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2)
dlsa rREFS, v0, rFP, 2
- daddu rPC, a1, CODEITEM_INSNS_OFFSET
lw v0, SHADOWFRAME_DEX_PC_OFFSET(a2)
- dlsa rPC, v0, rPC, 1
+ dlsa rPC, v0, a1, 1
EXPORT_PC
/* Starting ibase */
@@ -12241,11 +12240,10 @@
daddu a1, rFP, OFF_FP_SHADOWFRAME
jal MterpHandleException # (self, shadow_frame)
beqzc v0, MterpExceptionReturn # no local catch, back to caller.
- ld a0, OFF_FP_CODE_ITEM(rFP)
+ ld a0, OFF_FP_DEX_INSTRUCTIONS(rFP)
lwu a1, OFF_FP_DEX_PC(rFP)
REFRESH_IBASE
- daddu rPC, a0, CODEITEM_INSNS_OFFSET
- dlsa rPC, a1, rPC, 1 # generate new dex_pc_ptr
+ dlsa rPC, a1, a0, 1 # generate new dex_pc_ptr
/* Do we need to switch interpreters? */
jal MterpShouldSwitchInterpreters
bnezc v0, MterpFallback