commit 0955f7e470fb733aef07096536e9fba7c99250aa
author Matteo Franchin <matteo.franchin@arm.com> Fri May 23 17:32:52 2014 +0100
committer Matteo Franchin <matteo.franchin@arm.com> Thu May 29 15:42:34 2014 +0100
tree 9471cd03d79bac5abc9e6527f881c2a3eeacaa8b
parent c774bd435e95e537ca578486f687651fabe97008

AArch64: fixing some assertions.

Fixing some assertions while attempting to get libartd.so to work.
Fixing also the shift logic in LoadBaseIndexed() and StoreBaseIndexed().
This commit only fixes a part of the assertion issues.

Change-Id: I473194d4260dd59a8ee6d73114429728c977ee0e

compiler/dex/quick/ralloc_util.cc

diff --git a/compiler/dex/quick/ralloc_util.cc b/compiler/dex/quick/ralloc_util.cc
index e5ca460..59ae16e 100644
--- a/compiler/dex/quick/ralloc_util.cc
+++ b/compiler/dex/quick/ralloc_util.cc
@@ -406,6 +406,10 @@
   return res;
 }
 
+RegStorage Mir2Lir::AllocTempWord() {
+  return (Is64BitInstructionSet(cu_->instruction_set)) ? AllocTempWide() : AllocTemp();
+}
+
 RegStorage Mir2Lir::AllocTempSingle() {
   RegStorage res = AllocTempBody(reg_pool_->sp_regs_, &reg_pool_->next_sp_reg_, true);
   DCHECK(res.IsSingle()) << "Reg: 0x" << std::hex << res.GetRawBits();