commit 08f8d4cbc5e673a2a4b6eda08e3133c7bb626772
author Raghu Gandham <raghu.gandham@imgtec.com> Thu Aug 14 13:46:53 2014 -0700
committer Raghu Gandham <raghu.gandham@imgtec.com> Thu Aug 14 22:57:49 2014 -0700
tree dd692e094b6946c21ce7c1135fe6c4dc2abf1fdd
parent d684cbfbe8abfb9aea4de27687041243217295c7

[MIPS] Fix the code generated by GenSelectConst32

Change-Id: Icc1d0449566435200a10fa3ca5489f78d122bc89

compiler/dex/quick/mips/int_mips.cc

diff --git a/compiler/dex/quick/mips/int_mips.cc b/compiler/dex/quick/mips/int_mips.cc
index ea56989..95c1262 100644
--- a/compiler/dex/quick/mips/int_mips.cc
+++ b/compiler/dex/quick/mips/int_mips.cc
@@ -220,9 +220,9 @@
                                    int dest_reg_class) {
   // Implement as a branch-over.
   // TODO: Conditional move?
-  LoadConstant(rs_dest, false_val);  // Favors false.
-  LIR* ne_branchover = OpCmpBranch(code, left_op, right_op, NULL);
   LoadConstant(rs_dest, true_val);
+  LIR* ne_branchover = OpCmpBranch(code, left_op, right_op, NULL);
+  LoadConstant(rs_dest, false_val);
   LIR* target_label = NewLIR0(kPseudoTargetLabel);
   ne_branchover->target = target_label;
 }