AArch64 code alignment is 4 for OatWriter
OatWriter DCHECKs against ARM alignment, which is 8 and <= all
other architectures *except* AArch64, so that was fine before.
Change-Id: I55a11fe60cfbec889f2e8d8b0f489fe0930ebf6f
diff --git a/compiler/oat_writer.cc b/compiler/oat_writer.cc
index 2d45a2f..eff2425 100644
--- a/compiler/oat_writer.cc
+++ b/compiler/oat_writer.cc
@@ -345,6 +345,36 @@
return offset;
}
+static void DCheckCodeAlignment(size_t offset, InstructionSet isa) {
+ switch (isa) {
+ case kArm:
+ // Fall-through.
+ case kThumb2:
+ DCHECK_ALIGNED(offset, kArmAlignment);
+ break;
+
+ case kArm64:
+ DCHECK_ALIGNED(offset, kArm64Alignment);
+ break;
+
+ case kMips:
+ DCHECK_ALIGNED(offset, kMipsAlignment);
+ break;
+
+ case kX86_64:
+ // Fall-through.
+ case kX86:
+ DCHECK_ALIGNED(offset, kX86Alignment);
+ break;
+
+ case kNone:
+ // Use a DCHECK instead of FATAL so that in the non-debug case the whole switch can
+ // be optimized away.
+ DCHECK(false);
+ break;
+ }
+}
+
size_t OatWriter::InitOatCodeMethod(size_t offset, size_t oat_class_index,
size_t __attribute__((unused)) class_def_index,
size_t class_def_method_index,
@@ -376,7 +406,8 @@
} else {
CHECK(quick_code != nullptr);
offset = compiled_method->AlignCode(offset);
- DCHECK_ALIGNED(offset, kArmAlignment);
+ DCheckCodeAlignment(offset, compiled_method->GetInstructionSet());
+
uint32_t code_size = quick_code->size() * sizeof(uint8_t);
CHECK_NE(code_size, 0U);
uint32_t thumb_offset = compiled_method->CodeDelta();
@@ -826,7 +857,8 @@
relative_offset += aligned_code_delta;
DCHECK_OFFSET();
}
- DCHECK_ALIGNED(relative_offset, kArmAlignment);
+ DCheckCodeAlignment(relative_offset, compiled_method->GetInstructionSet());
+
uint32_t code_size = quick_code->size() * sizeof(uint8_t);
CHECK_NE(code_size, 0U);