ART: Introduce predicated vector instructions.
This CL introduces a minimal changes to the IR to support
autovectorization with use of predicated execution of SIMD
instructions (e.g. Arm SVE).
Test: test-art-target, test-art-host.
Change-Id: Ibb7c5520fec6b858fb29f0dde19ec65501831a3a
diff --git a/compiler/optimizing/graph_checker.cc b/compiler/optimizing/graph_checker.cc
index 95cfe3e..ece88a0 100644
--- a/compiler/optimizing/graph_checker.cc
+++ b/compiler/optimizing/graph_checker.cc
@@ -25,6 +25,7 @@
#include "base/bit_vector-inl.h"
#include "base/scoped_arena_allocator.h"
#include "base/scoped_arena_containers.h"
+#include "code_generator.h"
#include "handle.h"
#include "mirror/class.h"
#include "obj_ptr-inl.h"
@@ -1141,4 +1142,26 @@
}
}
+void GraphChecker::VisitVecOperation(HVecOperation* instruction) {
+ VisitInstruction(instruction);
+ if (codegen_ == nullptr) {
+ return;
+ }
+
+ if (!codegen_->SupportsPredicatedSIMD() && instruction->IsPredicated()) {
+ AddError(StringPrintf(
+ "%s %d must not be predicated.",
+ instruction->DebugName(),
+ instruction->GetId()));
+ }
+
+ if (codegen_->SupportsPredicatedSIMD() &&
+ (instruction->MustBePredicatedInPredicatedSIMDMode() != instruction->IsPredicated())) {
+ AddError(StringPrintf(
+ "%s %d predication mode is incorrect; see HVecOperation::MustBePredicated.",
+ instruction->DebugName(),
+ instruction->GetId()));
+ }
+}
+
} // namespace art