SVE: Extract Intermediate Address for SVE Vector Memory Operations
This patch introduces an optimization that extracts and factorizes
the "base + offset" common part for the address computation when
performing an SVE vector memory operation (VecStore/VecLoad).
With SVE enabled by default:
Test: ./art/test.py --simulate-arm64 --run-test --optimizing \
(With the VIXL simulator patch)
Test: ./art/test.py --target --64 --optimizing \
(On Arm FVP with SVE - See steps in test/README.arm_fvp.md)
Test: 527-checker-array-access, 655-checker-simd-arm.
Change-Id: Icd49e57d5550d1530445a94e5d49e217a999d06d
diff --git a/test/527-checker-array-access-simd/src/Main.java b/test/527-checker-array-access-simd/src/Main.java
index 173165a..a08b1f0 100644
--- a/test/527-checker-array-access-simd/src/Main.java
+++ b/test/527-checker-array-access-simd/src/Main.java
@@ -59,9 +59,11 @@
/// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile
/// CHECK-DAG: <<Index:i\d+>> Phi
/// CHECK-DAG: If
- /// CHECK-DAG: <<Load:d\d+>> VecLoad [<<Array>>,<<Index>>,<<LoopP>>]
+ /// CHECK-DAG: <<IntAddr1:i\d+>> IntermediateAddress [<<Array>>,{{i\d+}}]
+ /// CHECK-DAG: <<Load:d\d+>> VecLoad [<<IntAddr1>>,<<Index>>,<<LoopP>>]
/// CHECK-DAG: <<Add:d\d+>> VecAdd [<<Load>>,<<Repl>>,<<LoopP>>]
- /// CHECK-DAG: VecStore [<<Array>>,<<Index>>,<<Add>>,<<LoopP>>]
+ /// CHECK-DAG: <<IntAddr2:i\d+>> IntermediateAddress [<<Array>>,{{i\d+}}]
+ /// CHECK-DAG: VecStore [<<IntAddr2>>,<<Index>>,<<Add>>,<<LoopP>>]
//
/// CHECK-ELSE:
//
@@ -90,10 +92,10 @@
/// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile
/// CHECK-DAG: <<Index:i\d+>> Phi
/// CHECK-DAG: If
- /// CHECK-DAG: <<Load:d\d+>> VecLoad [<<Array>>,<<Index>>,<<LoopP>>]
+ /// CHECK-DAG: <<IntAddr:i\d+>> IntermediateAddress [<<Array>>,{{i\d+}}]
+ /// CHECK-DAG: <<Load:d\d+>> VecLoad [<<IntAddr>>,<<Index>>,<<LoopP>>]
/// CHECK-DAG: <<Add:d\d+>> VecAdd [<<Load>>,<<Repl>>,<<LoopP>>]
- /// CHECK-NOT: IntermediateAddress
- /// CHECK-DAG: VecStore [<<Array>>,<<Index>>,<<Add>>,<<LoopP>>]
+ /// CHECK-DAG: VecStore [<<IntAddr>>,<<Index>>,<<Add>>,<<LoopP>>]
//
/// CHECK-ELSE:
//
@@ -116,7 +118,6 @@
//
// IntermediateAddressIndex is not supported for SVE.
/// CHECK-NOT: IntermediateAddressIndex
- /// CHECK-NOT: IntermediateAddress
//
/// CHECK-ELSE:
//
@@ -168,9 +169,11 @@
/// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile
/// CHECK-DAG: <<Index:i\d+>> Phi
/// CHECK-DAG: If
- /// CHECK-DAG: <<Load:d\d+>> VecLoad [<<Array>>,<<Index>>,<<LoopP>>]
+ /// CHECK-DAG: <<IntAddr1:i\d+>> IntermediateAddress [<<Array>>,{{i\d+}}]
+ /// CHECK-DAG: <<Load:d\d+>> VecLoad [<<IntAddr1>>,<<Index>>,<<LoopP>>]
/// CHECK-DAG: <<Add:d\d+>> VecAdd [<<Load>>,<<Repl>>,<<LoopP>>]
- /// CHECK-DAG: VecStore [<<Array>>,<<Index>>,<<Add>>,<<LoopP>>]
+ /// CHECK-DAG: <<IntAddr2:i\d+>> IntermediateAddress [<<Array>>,{{i\d+}}]
+ /// CHECK-DAG: VecStore [<<IntAddr2>>,<<Index>>,<<Add>>,<<LoopP>>]
//
/// CHECK-ELSE:
//
@@ -199,10 +202,10 @@
/// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile
/// CHECK-DAG: <<Index:i\d+>> Phi
/// CHECK-DAG: If
- /// CHECK-DAG: <<Load:d\d+>> VecLoad [<<Array>>,<<Index>>,<<LoopP>>]
+ /// CHECK-DAG: <<IntAddr:i\d+>> IntermediateAddress [<<Array>>,{{i\d+}}]
+ /// CHECK-DAG: <<Load:d\d+>> VecLoad [<<IntAddr>>,<<Index>>,<<LoopP>>]
/// CHECK-DAG: <<Add:d\d+>> VecAdd [<<Load>>,<<Repl>>,<<LoopP>>]
- /// CHECK-NOT: IntermediateAddress
- /// CHECK-DAG: VecStore [<<Array>>,<<Index>>,<<Add>>,<<LoopP>>]
+ /// CHECK-DAG: VecStore [<<IntAddr>>,<<Index>>,<<Add>>,<<LoopP>>]
//
/// CHECK-ELSE:
//
@@ -224,7 +227,6 @@
//
// IntermediateAddressIndex is not supported for SVE.
/// CHECK-NOT: IntermediateAddressIndex
- /// CHECK-NOT: IntermediateAddress
//
/// CHECK-ELSE:
//
@@ -275,7 +277,8 @@
/// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile
/// CHECK-DAG: <<Index:i\d+>> Phi
/// CHECK-DAG: If
- /// CHECK-DAG: VecStore [<<Array>>,<<Index>>,<<Repl>>,<<LoopP>>]
+ /// CHECK-DAG: <<IntAddr:i\d+>> IntermediateAddress [<<Array>>,{{i\d+}}]
+ /// CHECK-DAG: VecStore [<<IntAddr>>,<<Index>>,<<Repl>>,<<LoopP>>]
//
/// CHECK-ELSE:
//
@@ -327,9 +330,11 @@
/// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile
/// CHECK-DAG: <<Index:i\d+>> Phi
/// CHECK-DAG: If
- /// CHECK-DAG: <<Load:d\d+>> VecLoad [<<Array1>>,<<Index>>,<<LoopP>>]
+ /// CHECK-DAG: <<IntAddr1:i\d+>> IntermediateAddress [<<Array1>>,{{i\d+}}]
+ /// CHECK-DAG: <<Load:d\d+>> VecLoad [<<IntAddr1>>,<<Index>>,<<LoopP>>]
/// CHECK-DAG: <<Cnv:d\d+>> VecCnv [<<Load>>,<<LoopP>>]
- /// CHECK-DAG: VecStore [<<Array2>>,<<Index>>,<<Cnv>>,<<LoopP>>]
+ /// CHECK-DAG: <<IntAddr2:i\d+>> IntermediateAddress [<<Array2>>,{{i\d+}}]
+ /// CHECK-DAG: VecStore [<<IntAddr2>>,<<Index>>,<<Cnv>>,<<LoopP>>]
//
/// CHECK-ELSE:
//
@@ -356,10 +361,11 @@
/// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile
/// CHECK-DAG: <<Index:i\d+>> Phi
/// CHECK-DAG: If
- /// CHECK-DAG: <<Load:d\d+>> VecLoad [<<Array1>>,<<Index>>,<<LoopP>>]
+ /// CHECK-DAG: <<IntAddr1:i\d+>> IntermediateAddress [<<Array1>>,{{i\d+}}]
+ /// CHECK-DAG: <<Load:d\d+>> VecLoad [<<IntAddr1>>,<<Index>>,<<LoopP>>]
/// CHECK-DAG: <<Cnv:d\d+>> VecCnv [<<Load>>,<<LoopP>>]
- /// CHECK-NOT: IntermediateAddress
- /// CHECK-DAG: VecStore [<<Array2>>,<<Index>>,<<Cnv>>,<<LoopP>>]
+ /// CHECK-DAG: <<IntAddr2:i\d+>> IntermediateAddress [<<Array2>>,{{i\d+}}]
+ /// CHECK-DAG: VecStore [<<IntAddr2>>,<<Index>>,<<Cnv>>,<<LoopP>>]
//
/// CHECK-ELSE:
//
@@ -381,7 +387,6 @@
//
// IntermediateAddressIndex is not supported for SVE.
/// CHECK-NOT: IntermediateAddressIndex
- /// CHECK-NOT: IntermediateAddress
//
/// CHECK-ELSE:
//