commit 0700b69cb0c81c3590726be7fbe5b98531cec76b
author Raphael Gault <raphael.gault@linaro.org> Wed Sep 30 08:33:10 2020 +0000
committer Nicolas Geoffray <ngeoffray@google.com> Mon Sep 06 08:58:50 2021 +0000
tree 9699ae3c78a2c7546918ba03aa43b0306d4f48a5
parent 6194403a984dd814f01e6f7c6b270342d760388d

SVE: Extract Intermediate Address for SVE Vector Memory Operations

This patch introduces an optimization that extracts and factorizes
the "base + offset" common part for the address computation when
performing an SVE vector memory operation (VecStore/VecLoad).

With SVE enabled by default:

Test: ./art/test.py --simulate-arm64 --run-test --optimizing \
(With the VIXL simulator patch)

Test: ./art/test.py --target --64 --optimizing \
(On Arm FVP with SVE - See steps in test/README.arm_fvp.md)

Test: 527-checker-array-access, 655-checker-simd-arm.

Change-Id: Icd49e57d5550d1530445a94e5d49e217a999d06d

compiler/optimizing/code_generator_arm64.cc

diff --git a/compiler/optimizing/code_generator_arm64.cc b/compiler/optimizing/code_generator_arm64.cc
index e1a4718..7401f0d 100644
--- a/compiler/optimizing/code_generator_arm64.cc
+++ b/compiler/optimizing/code_generator_arm64.cc
@@ -6909,9 +6909,7 @@
   Register base = InputRegisterAt(instruction, 0);
   Location index = locations->InAt(1);
 
-  // TODO: Support intermediate address sharing for SVE accesses.
   DCHECK(!instruction->InputAt(1)->IsIntermediateAddressIndex());
-  DCHECK(!instruction->InputAt(0)->IsIntermediateAddress());
   DCHECK(!index.IsConstant());
 
   uint32_t offset = is_string_char_at
@@ -6919,6 +6917,10 @@
       : mirror::Array::DataOffset(size).Uint32Value();
   size_t shift = ComponentSizeShiftWidth(size);
 
+  if (instruction->InputAt(0)->IsIntermediateAddress()) {
+    return SVEMemOperand(base.X(), XRegisterFrom(index), LSL, shift);
+  }
+
   *scratch = temps_scope->AcquireSameSizeAs(base);
   __ Add(*scratch, base, offset);
   return SVEMemOperand(scratch->X(), XRegisterFrom(index), LSL, shift);