commit 0646da7c04e4744c84d1b0a03df33ccae1d6d477
author Chris Larsen <chris.larsen@imgtec.com> Tue Sep 22 16:02:40 2015 -0700
committer Andreas Gampe <agampe@google.com> Mon Oct 19 08:11:56 2015 -0700
tree bde7904026208c57da81a205c3cbb499cfbf82d2
parent 45513eb694fe55cf02ca6e8f0884621a6c3f6268

MIPS64: Add intrinsics support for trailing zeros

- int java.lang.Integer.numberOfTrailingZeros(int i)
- int java.lang.Long.numberOfTrailingZeros(long i)

Change-Id: I0fc1c2629738de9047313b6511b490639eef68f3

compiler/optimizing/intrinsics_mips64.cc

diff --git a/compiler/optimizing/intrinsics_mips64.cc b/compiler/optimizing/intrinsics_mips64.cc
index 59125ff..a3121a9 100644
--- a/compiler/optimizing/intrinsics_mips64.cc
+++ b/compiler/optimizing/intrinsics_mips64.cc
@@ -272,7 +272,7 @@
   GenReverseBytes(invoke->GetLocations(), Primitive::kPrimShort, GetAssembler());
 }
 
-static void GenCountZeroes(LocationSummary* locations, bool is64bit, Mips64Assembler* assembler) {
+static void GenNumberOfLeadingZeroes(LocationSummary* locations, bool is64bit, Mips64Assembler* assembler) {
   GpuRegister in  = locations->InAt(0).AsRegister<GpuRegister>();
   GpuRegister out = locations->Out().AsRegister<GpuRegister>();
 
@@ -289,7 +289,7 @@
 }
 
 void IntrinsicCodeGeneratorMIPS64::VisitIntegerNumberOfLeadingZeros(HInvoke* invoke) {
-  GenCountZeroes(invoke->GetLocations(), false, GetAssembler());
+  GenNumberOfLeadingZeroes(invoke->GetLocations(), false, GetAssembler());
 }
 
 // int java.lang.Long.numberOfLeadingZeros(long i)
@@ -298,7 +298,42 @@
 }
 
 void IntrinsicCodeGeneratorMIPS64::VisitLongNumberOfLeadingZeros(HInvoke* invoke) {
-  GenCountZeroes(invoke->GetLocations(), true, GetAssembler());
+  GenNumberOfLeadingZeroes(invoke->GetLocations(), true, GetAssembler());
+}
+
+static void GenNumberOfTrailingZeroes(LocationSummary* locations, bool is64bit, Mips64Assembler* assembler) {
+  Location in = locations->InAt(0);
+  Location out = locations->Out();
+
+  if (is64bit) {
+    __ Dsbh(out.AsRegister<GpuRegister>(), in.AsRegister<GpuRegister>());
+    __ Dshd(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>());
+    __ Dbitswap(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>());
+    __ Dclz(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>());
+  } else {
+    __ Rotr(out.AsRegister<GpuRegister>(), in.AsRegister<GpuRegister>(), 16);
+    __ Wsbh(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>());
+    __ Bitswap(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>());
+    __ Clz(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>());
+  }
+}
+
+// int java.lang.Integer.numberOfTrailingZeros(int i)
+void IntrinsicLocationsBuilderMIPS64::VisitIntegerNumberOfTrailingZeros(HInvoke* invoke) {
+  CreateIntToIntLocations(arena_, invoke);
+}
+
+void IntrinsicCodeGeneratorMIPS64::VisitIntegerNumberOfTrailingZeros(HInvoke* invoke) {
+  GenNumberOfTrailingZeroes(invoke->GetLocations(), false, GetAssembler());
+}
+
+// int java.lang.Long.numberOfTrailingZeros(long i)
+void IntrinsicLocationsBuilderMIPS64::VisitLongNumberOfTrailingZeros(HInvoke* invoke) {
+  CreateIntToIntLocations(arena_, invoke);
+}
+
+void IntrinsicCodeGeneratorMIPS64::VisitLongNumberOfTrailingZeros(HInvoke* invoke) {
+  GenNumberOfTrailingZeroes(invoke->GetLocations(), true, GetAssembler());
 }
 
 static void GenReverse(LocationSummary* locations,
@@ -1368,10 +1403,8 @@
 UNIMPLEMENTED_INTRINSIC(StringEquals)
 UNIMPLEMENTED_INTRINSIC(LongRotateLeft)
 UNIMPLEMENTED_INTRINSIC(LongRotateRight)
-UNIMPLEMENTED_INTRINSIC(LongNumberOfTrailingZeros)
 UNIMPLEMENTED_INTRINSIC(IntegerRotateLeft)
 UNIMPLEMENTED_INTRINSIC(IntegerRotateRight)
-UNIMPLEMENTED_INTRINSIC(IntegerNumberOfTrailingZeros)
 
 UNIMPLEMENTED_INTRINSIC(ReferenceGetReferent)
 UNIMPLEMENTED_INTRINSIC(StringGetCharsNoCheck)