commit 05792b98980741111b4d0a24d68cff2a8e070a3a
author Vladimir Marko <vmarko@google.com> Mon Aug 03 11:56:49 2015 +0100
committer Vladimir Marko <vmarko@google.com> Thu Sep 03 17:30:57 2015 +0100
tree bad79a387bcbdaefc87c07b388099960ca9caff3
parent c26b4512a01d46756683a4f5e186a0b7f397f251

ART: Move DexCache arrays to native.

This CL has a companion CL in libcore/
    https://android-review.googlesource.com/162985

Change-Id: Icbc9e20ad1b565e603195b12714762bb446515fa

compiler/dex/quick/mips/call_mips.cc

diff --git a/compiler/dex/quick/mips/call_mips.cc b/compiler/dex/quick/mips/call_mips.cc
index 853980d..8863c05 100644
--- a/compiler/dex/quick/mips/call_mips.cc
+++ b/compiler/dex/quick/mips/call_mips.cc
@@ -415,10 +415,11 @@
  * Bit of a hack here - in the absence of a real scheduling pass,
  * emit the next instruction in static & direct invoke sequences.
  */
-static int NextSDCallInsn(CompilationUnit* cu, CallInfo* info, int state,
-                          const MethodReference& target_method, uint32_t, uintptr_t direct_code,
-                          uintptr_t direct_method, InvokeType type) {
-  Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get());
+int MipsMir2Lir::MipsNextSDCallInsn(CompilationUnit* cu, CallInfo* info, int state,
+                                    const MethodReference& target_method, uint32_t,
+                                    uintptr_t direct_code, uintptr_t direct_method,
+                                    InvokeType type) {
+  MipsMir2Lir* cg = static_cast<MipsMir2Lir*>(cu->cg.get());
   if (info->string_init_offset != 0) {
     RegStorage arg0_ref = cg->TargetReg(kArg0, kRef);
     switch (state) {
@@ -469,10 +470,12 @@
         cg->LoadCurrMethodDirect(arg0_ref);
         break;
       case 1:  // Get method->dex_cache_resolved_methods_
-        cg->LoadRefDisp(arg0_ref,
-                        ArtMethod::DexCacheResolvedMethodsOffset().Int32Value(),
-                        arg0_ref,
-                        kNotVolatile);
+        cg->LoadBaseDisp(arg0_ref,
+                         ArtMethod::DexCacheResolvedMethodsOffset(
+                             cu->target64 ? kMips64PointerSize : kMipsPointerSize).Int32Value(),
+                         arg0_ref,
+                         cu->target64 ? k64 : k32,
+                         kNotVolatile);
         // Set up direct code if known.
         if (direct_code != 0) {
           if (direct_code != static_cast<uintptr_t>(-1)) {
@@ -492,8 +495,9 @@
         CHECK_EQ(cu->dex_file, target_method.dex_file);
         const size_t pointer_size = GetInstructionSetPointerSize(cu->instruction_set);
         cg->LoadWordDisp(arg0_ref,
-                         mirror::Array::DataOffset(pointer_size).Uint32Value() +
-                         target_method.dex_method_index * pointer_size, arg0_ref);
+                         cg->GetCachePointerOffset(target_method.dex_method_index,
+                                                   pointer_size),
+                         arg0_ref);
         break;
       }
       case 3:  // Grab the code from the method*
@@ -512,7 +516,7 @@
 }
 
 NextCallInsn MipsMir2Lir::GetNextSDCallInsn() {
-  return NextSDCallInsn;
+  return MipsNextSDCallInsn;
 }
 
 LIR* MipsMir2Lir::GenCallInsn(const MirMethodLoweringInfo& method_info ATTRIBUTE_UNUSED) {

compiler/dex/quick/mips/codegen_mips.h

diff --git a/compiler/dex/quick/mips/codegen_mips.h b/compiler/dex/quick/mips/codegen_mips.h
index 2173253..378b9a0 100644
--- a/compiler/dex/quick/mips/codegen_mips.h
+++ b/compiler/dex/quick/mips/codegen_mips.h
@@ -269,6 +269,11 @@
   const bool fpuIs32Bit_;
 
  private:
+  static int MipsNextSDCallInsn(CompilationUnit* cu, CallInfo* info, int state,
+                                const MethodReference& target_method, uint32_t,
+                                uintptr_t direct_code, uintptr_t direct_method,
+                                InvokeType type);
+
   void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
   void GenAddLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
   void GenSubLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);