Move disassembler out of runtime.
Bug: 9877500.
Change-Id: Ica6d9f5ecfd20c86e5230a2213827bd78cd29a29
diff --git a/disassembler/Android.mk b/disassembler/Android.mk
new file mode 100644
index 0000000..f8001a4
--- /dev/null
+++ b/disassembler/Android.mk
@@ -0,0 +1,120 @@
+#
+# Copyright (C) 2012 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+include art/build/Android.common.mk
+
+LIBART_DISASSEMBLER_SRC_FILES := \
+ disassembler.cc \
+ disassembler_arm.cc \
+ disassembler_mips.cc \
+ disassembler_x86.cc
+
+# $(1): target or host
+# $(2): ndebug or debug
+define build-libart-disassembler
+ ifneq ($(1),target)
+ ifneq ($(1),host)
+ $$(error expected target or host for argument 1, received $(1))
+ endif
+ endif
+ ifneq ($(2),ndebug)
+ ifneq ($(2),debug)
+ $$(error expected ndebug or debug for argument 2, received $(2))
+ endif
+ endif
+
+ art_target_or_host := $(1)
+ art_ndebug_or_debug := $(2)
+
+ include $(CLEAR_VARS)
+ ifeq ($$(art_target_or_host),target)
+ include external/stlport/libstlport.mk
+ else
+ LOCAL_IS_HOST_MODULE := true
+ endif
+ LOCAL_CPP_EXTENSION := $(ART_CPP_EXTENSION)
+ ifeq ($$(art_ndebug_or_debug),ndebug)
+ LOCAL_MODULE := libart-disassembler
+ else # debug
+ LOCAL_MODULE := libartd-disassembler
+ endif
+
+ LOCAL_MODULE_TAGS := optional
+ LOCAL_MODULE_CLASS := SHARED_LIBRARIES
+
+ LOCAL_SRC_FILES := $$(LIBART_DISASSEMBLER_SRC_FILES)
+
+ GENERATED_SRC_DIR := $$(call intermediates-dir-for,$$(LOCAL_MODULE_CLASS),$$(LOCAL_MODULE),$$(LOCAL_IS_HOST_MODULE),)
+
+ ifeq ($$(art_target_or_host),target)
+ LOCAL_CLANG := $(ART_TARGET_CLANG)
+ LOCAL_CFLAGS += $(ART_TARGET_CFLAGS)
+ else # host
+ LOCAL_CLANG := $(ART_HOST_CLANG)
+ LOCAL_CFLAGS += $(ART_HOST_CFLAGS)
+ endif
+
+ LOCAL_SHARED_LIBRARIES += liblog
+ ifeq ($$(art_ndebug_or_debug),debug)
+ ifeq ($$(art_target_or_host),target)
+ LOCAL_CFLAGS += $(ART_TARGET_DEBUG_CFLAGS)
+ else # host
+ LOCAL_CFLAGS += $(ART_HOST_DEBUG_CFLAGS)
+ endif
+ LOCAL_SHARED_LIBRARIES += libartd
+ else
+ ifeq ($$(art_target_or_host),target)
+ LOCAL_CFLAGS += $(ART_TARGET_NON_DEBUG_CFLAGS)
+ else # host
+ LOCAL_CFLAGS += $(ART_HOST_NON_DEBUG_CFLAGS)
+ endif
+ LOCAL_SHARED_LIBRARIES += libart
+ endif
+
+ LOCAL_C_INCLUDES += $(ART_C_INCLUDES) art/runtime
+
+ LOCAL_ADDITIONAL_DEPENDENCIES := art/build/Android.common.mk
+ LOCAL_ADDITIONAL_DEPENDENCIES += $(LOCAL_PATH)/Android.mk
+ ifeq ($$(art_target_or_host),target)
+ LOCAL_SHARED_LIBRARIES += libcutils
+ include $(LLVM_GEN_INTRINSICS_MK)
+ include $(LLVM_DEVICE_BUILD_MK)
+ include $(BUILD_SHARED_LIBRARY)
+ else # host
+ LOCAL_STATIC_LIBRARIES += libcutils
+ include $(LLVM_GEN_INTRINSICS_MK)
+ include $(LLVM_HOST_BUILD_MK)
+ include $(BUILD_HOST_SHARED_LIBRARY)
+ endif
+endef
+
+ifeq ($(ART_BUILD_TARGET_NDEBUG),true)
+ $(eval $(call build-libart-disassembler,target,ndebug))
+endif
+ifeq ($(ART_BUILD_TARGET_DEBUG),true)
+ $(eval $(call build-libart-disassembler,target,debug))
+endif
+ifeq ($(WITH_HOST_DALVIK),true)
+ # We always build dex2oat and dependencies, even if the host build is otherwise disabled, since they are used to cross compile for the target.
+ ifeq ($(ART_BUILD_NDEBUG),true)
+ $(eval $(call build-libart-disassembler,host,ndebug))
+ endif
+ ifeq ($(ART_BUILD_DEBUG),true)
+ $(eval $(call build-libart-disassembler,host,debug))
+ endif
+endif
diff --git a/disassembler/disassembler.cc b/disassembler/disassembler.cc
new file mode 100644
index 0000000..0670835
--- /dev/null
+++ b/disassembler/disassembler.cc
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "disassembler.h"
+
+#include <iostream>
+
+#include "base/logging.h"
+#include "disassembler_arm.h"
+#include "disassembler_mips.h"
+#include "disassembler_x86.h"
+
+namespace art {
+
+Disassembler* Disassembler::Create(InstructionSet instruction_set) {
+ if (instruction_set == kArm || instruction_set == kThumb2) {
+ return new arm::DisassemblerArm();
+ } else if (instruction_set == kMips) {
+ return new mips::DisassemblerMips();
+ } else if (instruction_set == kX86) {
+ return new x86::DisassemblerX86();
+ } else {
+ UNIMPLEMENTED(FATAL) << "no disassembler for " << instruction_set;
+ return NULL;
+ }
+}
+
+} // namespace art
diff --git a/disassembler/disassembler.h b/disassembler/disassembler.h
new file mode 100644
index 0000000..7547ab7
--- /dev/null
+++ b/disassembler/disassembler.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ART_DISASSEMBLER_DISASSEMBLER_H_
+#define ART_DISASSEMBLER_DISASSEMBLER_H_
+
+#include <stdint.h>
+
+#include <iosfwd>
+
+#include "base/macros.h"
+#include "instruction_set.h"
+
+namespace art {
+
+class Disassembler {
+ public:
+ static Disassembler* Create(InstructionSet instruction_set);
+ virtual ~Disassembler() {}
+
+ // Dump a single instruction returning the length of that instruction.
+ virtual size_t Dump(std::ostream& os, const uint8_t* begin) = 0;
+ // Dump instructions within a range.
+ virtual void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) = 0;
+
+ protected:
+ Disassembler() {}
+
+ private:
+ DISALLOW_COPY_AND_ASSIGN(Disassembler);
+};
+
+} // namespace art
+
+#endif // ART_DISASSEMBLER_DISASSEMBLER_H_
diff --git a/disassembler/disassembler_arm.cc b/disassembler/disassembler_arm.cc
new file mode 100644
index 0000000..879d3ac
--- /dev/null
+++ b/disassembler/disassembler_arm.cc
@@ -0,0 +1,1359 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "disassembler_arm.h"
+
+#include <iostream>
+
+#include "base/logging.h"
+#include "base/stringprintf.h"
+#include "thread.h"
+
+namespace art {
+namespace arm {
+
+DisassemblerArm::DisassemblerArm() {
+}
+
+size_t DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin) {
+ if ((reinterpret_cast<intptr_t>(begin) & 1) == 0) {
+ DumpArm(os, begin);
+ return 4;
+ } else {
+ // remove thumb specifier bits
+ begin = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(begin) & ~1);
+ return DumpThumb16(os, begin);
+ }
+}
+
+void DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) {
+ if ((reinterpret_cast<intptr_t>(begin) & 1) == 0) {
+ for (const uint8_t* cur = begin; cur < end; cur += 4) {
+ DumpArm(os, cur);
+ }
+ } else {
+ // remove thumb specifier bits
+ begin = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(begin) & ~1);
+ end = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(end) & ~1);
+ for (const uint8_t* cur = begin; cur < end;) {
+ cur += DumpThumb16(os, cur);
+ }
+ }
+}
+
+static const char* kConditionCodeNames[] = {
+ "eq", // 0000 - equal
+ "ne", // 0001 - not-equal
+ "cs", // 0010 - carry-set, greater than, equal or unordered
+ "cc", // 0011 - carry-clear, less than
+ "mi", // 0100 - minus, negative
+ "pl", // 0101 - plus, positive or zero
+ "vs", // 0110 - overflow
+ "vc", // 0111 - no overflow
+ "hi", // 1000 - unsigned higher
+ "ls", // 1001 - unsigned lower or same
+ "ge", // 1010 - signed greater than or equal
+ "lt", // 1011 - signed less than
+ "gt", // 1100 - signed greater than
+ "le", // 1101 - signed less than or equal
+ "", // 1110 - always
+ "nv", // 1111 - never (mostly obsolete, but might be a clue that we're mistranslating)
+};
+
+void DisassemblerArm::DumpCond(std::ostream& os, uint32_t cond) {
+ if (cond < 15) {
+ os << kConditionCodeNames[cond];
+ } else {
+ os << "Unexpected condition: " << cond;
+ }
+}
+
+void DisassemblerArm::DumpBranchTarget(std::ostream& os, const uint8_t* instr_ptr, int32_t imm32) {
+ os << StringPrintf("%+d (%p)", imm32, instr_ptr + imm32);
+}
+
+static uint32_t ReadU16(const uint8_t* ptr) {
+ return ptr[0] | (ptr[1] << 8);
+}
+
+static uint32_t ReadU32(const uint8_t* ptr) {
+ return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24);
+}
+
+static const char* kDataProcessingOperations[] = {
+ "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc",
+ "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn",
+};
+
+static const char* kThumbDataProcessingOperations[] = {
+ "and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror",
+ "tst", "rsb", "cmp", "cmn", "orr", "mul", "bic", "mvn",
+};
+
+struct ArmRegister {
+ explicit ArmRegister(uint32_t r) : r(r) { CHECK_LE(r, 15U); }
+ ArmRegister(uint32_t instruction, uint32_t at_bit) : r((instruction >> at_bit) & 0xf) { CHECK_LE(r, 15U); }
+ uint32_t r;
+};
+std::ostream& operator<<(std::ostream& os, const ArmRegister& r) {
+ if (r.r == 13) {
+ os << "sp";
+ } else if (r.r == 14) {
+ os << "lr";
+ } else if (r.r == 15) {
+ os << "pc";
+ } else {
+ os << "r" << r.r;
+ }
+ return os;
+}
+
+struct ThumbRegister : ArmRegister {
+ ThumbRegister(uint16_t instruction, uint16_t at_bit) : ArmRegister((instruction >> at_bit) & 0x7) {}
+};
+
+struct Rm {
+ explicit Rm(uint32_t instruction) : shift((instruction >> 4) & 0xff), rm(instruction & 0xf) {}
+ uint32_t shift;
+ ArmRegister rm;
+};
+std::ostream& operator<<(std::ostream& os, const Rm& r) {
+ os << r.rm;
+ if (r.shift != 0) {
+ os << "-shift-" << r.shift; // TODO
+ }
+ return os;
+}
+
+struct ShiftedImmediate {
+ explicit ShiftedImmediate(uint32_t instruction) {
+ uint32_t rotate = ((instruction >> 8) & 0xf);
+ uint32_t imm = (instruction & 0xff);
+ value = (imm >> (2 * rotate)) | (imm << (32 - (2 * rotate)));
+ }
+ uint32_t value;
+};
+std::ostream& operator<<(std::ostream& os, const ShiftedImmediate& rhs) {
+ os << "#" << rhs.value;
+ return os;
+}
+
+struct RegisterList {
+ explicit RegisterList(uint32_t instruction) : register_list(instruction & 0xffff) {}
+ uint32_t register_list;
+};
+std::ostream& operator<<(std::ostream& os, const RegisterList& rhs) {
+ if (rhs.register_list == 0) {
+ os << "<no register list?>";
+ return os;
+ }
+ os << "{";
+ bool first = true;
+ for (size_t i = 0; i < 16; i++) {
+ if ((rhs.register_list & (1 << i)) != 0) {
+ if (first) {
+ first = false;
+ } else {
+ os << ", ";
+ }
+ os << ArmRegister(i);
+ }
+ }
+ os << "}";
+ return os;
+}
+
+void DisassemblerArm::DumpArm(std::ostream& os, const uint8_t* instr_ptr) {
+ uint32_t instruction = ReadU32(instr_ptr);
+ uint32_t cond = (instruction >> 28) & 0xf;
+ uint32_t op1 = (instruction >> 25) & 0x7;
+ std::string opcode;
+ std::string suffixes;
+ std::ostringstream args;
+ switch (op1) {
+ case 0:
+ case 1: // Data processing instructions.
+ {
+ if ((instruction & 0x0ff000f0) == 0x01200070) { // BKPT
+ opcode = "bkpt";
+ uint32_t imm12 = (instruction >> 8) & 0xfff;
+ uint32_t imm4 = (instruction & 0xf);
+ args << '#' << ((imm12 << 4) | imm4);
+ break;
+ }
+ if ((instruction & 0x0fffffd0) == 0x012fff10) { // BX and BLX (register)
+ opcode = (((instruction >> 5) & 1) ? "blx" : "bx");
+ args << ArmRegister(instruction & 0xf);
+ break;
+ }
+ bool i = (instruction & (1 << 25)) != 0;
+ bool s = (instruction & (1 << 20)) != 0;
+ uint32_t op = (instruction >> 21) & 0xf;
+ opcode = kDataProcessingOperations[op];
+ bool implicit_s = ((op & ~3) == 8); // TST, TEQ, CMP, and CMN.
+ if (implicit_s) {
+ // Rd is unused (and not shown), and we don't show the 's' suffix either.
+ } else {
+ if (s) {
+ suffixes += 's';
+ }
+ args << ArmRegister(instruction, 12) << ", ";
+ }
+ if (i) {
+ args << ArmRegister(instruction, 16) << ", " << ShiftedImmediate(instruction);
+ } else {
+ args << Rm(instruction);
+ }
+ }
+ break;
+ case 2: // Load/store word and unsigned byte.
+ {
+ bool p = (instruction & (1 << 24)) != 0;
+ bool b = (instruction & (1 << 22)) != 0;
+ bool w = (instruction & (1 << 21)) != 0;
+ bool l = (instruction & (1 << 20)) != 0;
+ opcode = StringPrintf("%s%s", (l ? "ldr" : "str"), (b ? "b" : ""));
+ args << ArmRegister(instruction, 12) << ", ";
+ ArmRegister rn(instruction, 16);
+ if (rn.r == 0xf) {
+ UNIMPLEMENTED(FATAL) << "literals";
+ } else {
+ bool wback = !p || w;
+ uint32_t offset = (instruction & 0xfff);
+ if (p && !wback) {
+ args << "[" << rn << ", #" << offset << "]";
+ } else if (p && wback) {
+ args << "[" << rn << ", #" << offset << "]!";
+ } else if (!p && wback) {
+ args << "[" << rn << "], #" << offset;
+ } else {
+ LOG(FATAL) << p << " " << w;
+ }
+ if (rn.r == 9) {
+ args << " ; ";
+ Thread::DumpThreadOffset(args, offset, 4);
+ }
+ }
+ }
+ break;
+ case 4: // Load/store multiple.
+ {
+ bool p = (instruction & (1 << 24)) != 0;
+ bool u = (instruction & (1 << 23)) != 0;
+ bool w = (instruction & (1 << 21)) != 0;
+ bool l = (instruction & (1 << 20)) != 0;
+ opcode = StringPrintf("%s%c%c", (l ? "ldm" : "stm"), (u ? 'i' : 'd'), (p ? 'b' : 'a'));
+ args << ArmRegister(instruction, 16) << (w ? "!" : "") << ", " << RegisterList(instruction);
+ }
+ break;
+ case 5: // Branch/branch with link.
+ {
+ bool bl = (instruction & (1 << 24)) != 0;
+ opcode = (bl ? "bl" : "b");
+ int32_t imm26 = (instruction & 0xffffff) << 2;
+ int32_t imm32 = (imm26 << 6) >> 6; // Sign extend.
+ DumpBranchTarget(args, instr_ptr + 8, imm32);
+ }
+ break;
+ default:
+ opcode = "???";
+ break;
+ }
+ opcode += kConditionCodeNames[cond];
+ opcode += suffixes;
+ // TODO: a more complete ARM disassembler could generate wider opcodes.
+ os << StringPrintf("%p: %08x\t%-7s ", instr_ptr, instruction, opcode.c_str()) << args.str() << '\n';
+}
+
+size_t DisassemblerArm::DumpThumb32(std::ostream& os, const uint8_t* instr_ptr) {
+ uint32_t instr = (ReadU16(instr_ptr) << 16) | ReadU16(instr_ptr + 2);
+ // |111|1 1|1000000|0000|1111110000000000|
+ // |5 3|2 1|0987654|3 0|5 0 5 0|
+ // |---|---|-------|----|----------------|
+ // |332|2 2|2222222|1111|1111110000000000|
+ // |1 9|8 7|6543210|9 6|5 0 5 0|
+ // |---|---|-------|----|----------------|
+ // |111|op1| op2 | | |
+ uint32_t op1 = (instr >> 27) & 3;
+ if (op1 == 0) {
+ return DumpThumb16(os, instr_ptr);
+ }
+
+ uint32_t op2 = (instr >> 20) & 0x7F;
+ std::ostringstream opcode;
+ std::ostringstream args;
+ switch (op1) {
+ case 0:
+ break;
+ case 1:
+ if ((op2 & 0x64) == 0) { // 00x x0xx
+ // |111|11|10|00|0|00|0000|1111110000000000|
+ // |5 3|21|09|87|6|54|3 0|5 0 5 0|
+ // |---|--|--|--|-|--|----|----------------|
+ // |332|22|22|22|2|22|1111|1111110000000000|
+ // |1 9|87|65|43|2|10|9 6|5 0 5 0|
+ // |---|--|--|--|-|--|----|----------------|
+ // |111|01|00|op|0|WL| Rn | |
+ // |111|01| op2 | | |
+ // STM - 111 01 00-01-0-W0 nnnn rrrrrrrrrrrrrrrr
+ // LDM - 111 01 00-01-0-W1 nnnn rrrrrrrrrrrrrrrr
+ // PUSH- 111 01 00-01-0-10 1101 0M0rrrrrrrrrrrrr
+ // POP - 111 01 00-01-0-11 1101 PM0rrrrrrrrrrrrr
+ uint32_t op = (instr >> 23) & 3;
+ uint32_t W = (instr >> 21) & 1;
+ uint32_t L = (instr >> 20) & 1;
+ ArmRegister Rn(instr, 16);
+ if (op == 1 || op == 2) {
+ if (op == 1) {
+ if (L == 0) {
+ opcode << "stm";
+ args << Rn << (W == 0 ? "" : "!") << ", ";
+ } else {
+ if (Rn.r != 13) {
+ opcode << "ldm";
+ args << Rn << (W == 0 ? "" : "!") << ", ";
+ } else {
+ opcode << "pop";
+ }
+ }
+ } else {
+ if (L == 0) {
+ if (Rn.r != 13) {
+ opcode << "stmdb";
+ args << Rn << (W == 0 ? "" : "!") << ", ";
+ } else {
+ opcode << "push";
+ }
+ } else {
+ opcode << "ldmdb";
+ args << Rn << (W == 0 ? "" : "!") << ", ";
+ }
+ }
+ args << RegisterList(instr);
+ }
+ } else if ((op2 & 0x64) == 4) { // 00x x1xx
+ uint32_t op3 = (instr >> 23) & 3;
+ uint32_t op4 = (instr >> 20) & 3;
+ // uint32_t op5 = (instr >> 4) & 0xF;
+ ArmRegister Rn(instr, 16);
+ ArmRegister Rt(instr, 12);
+ uint32_t imm8 = instr & 0xFF;
+ if (op3 == 0 && op4 == 0) { // STREX
+ ArmRegister Rd(instr, 8);
+ opcode << "strex";
+ args << Rd << ", " << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]";
+ } else if (op3 == 0 && op4 == 1) { // LDREX
+ opcode << "ldrex";
+ args << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]";
+ }
+ } else if ((op2 & 0x60) == 0x20) { // 01x xxxx
+ // Data-processing (shifted register)
+ // |111|1110|0000|0|0000|1111|1100|00|00|0000|
+ // |5 3|2109|8765|4|3 0|5 |10 8|7 |5 |3 0|
+ // |---|----|----|-|----|----|----|--|--|----|
+ // |332|2222|2222|2|1111|1111|1100|00|00|0000|
+ // |1 9|8765|4321|0|9 6|5 |10 8|7 |5 |3 0|
+ // |---|----|----|-|----|----|----|--|--|----|
+ // |111|0101| op3|S| Rn |imm3| Rd |i2|ty| Rm |
+ uint32_t op3 = (instr >> 21) & 0xF;
+ uint32_t S = (instr >> 20) & 1;
+ uint32_t imm3 = ((instr >> 12) & 0x7);
+ uint32_t imm2 = ((instr >> 6) & 0x3);
+ uint32_t imm5 = ((imm3 << 3) | imm2) & 0x1F;
+ uint32_t shift_type = ((instr >> 4) & 0x2);
+ ArmRegister Rd(instr, 8);
+ ArmRegister Rn(instr, 16);
+ ArmRegister Rm(instr, 0);
+ switch (op3) {
+ case 0x0:
+ if (Rd.r != 0xF) {
+ opcode << "and";
+ } else {
+ if (S != 1U) {
+ opcode << "UNKNOWN TST-" << S;
+ break;
+ }
+ opcode << "tst";
+ S = 0; // don't print 's'
+ }
+ break;
+ case 0x1: opcode << "bic"; break;
+ case 0x2:
+ if (Rn.r != 0xF) {
+ opcode << "orr";
+ } else {
+ // TODO: use canonical form if there is a shift (lsl, ...).
+ opcode << "mov";
+ }
+ break;
+ case 0x3:
+ if (Rn.r != 0xF) {
+ opcode << "orn";
+ } else {
+ opcode << "mvn";
+ }
+ break;
+ case 0x4:
+ if (Rd.r != 0xF) {
+ opcode << "eor";
+ } else {
+ if (S != 1U) {
+ opcode << "UNKNOWN TEQ-" << S;
+ break;
+ }
+ opcode << "teq";
+ S = 0; // don't print 's'
+ }
+ break;
+ case 0x6: opcode << "pkh"; break;
+ case 0x8:
+ if (Rd.r != 0xF) {
+ opcode << "add";
+ } else {
+ if (S != 1U) {
+ opcode << "UNKNOWN CMN-" << S;
+ break;
+ }
+ opcode << "cmn";
+ S = 0; // don't print 's'
+ }
+ break;
+ case 0xA: opcode << "adc"; break;
+ case 0xB: opcode << "sbc"; break;
+ case 0xD:
+ if (Rd.r != 0xF) {
+ opcode << "sub";
+ } else {
+ if (S != 1U) {
+ opcode << "UNKNOWN CMP-" << S;
+ break;
+ }
+ opcode << "cmp";
+ S = 0; // don't print 's'
+ }
+ break;
+ case 0xE: opcode << "rsb"; break;
+ default: opcode << "UNKNOWN DPSR-" << op3; break;
+ }
+
+ if (S == 1) {
+ opcode << "s";
+ }
+ opcode << ".w";
+
+ if (Rd.r != 0xF) {
+ args << Rd << ", ";
+ }
+ if (Rn.r != 0xF) {
+ args << Rn << ", ";
+ }
+ args << Rm;
+
+ // Shift operand.
+ bool noShift = (imm5 == 0 && shift_type != 0x3);
+ if (!noShift) {
+ args << ", ";
+ switch (shift_type) {
+ case 0x0: args << "lsl"; break;
+ case 0x1: args << "lsr"; break;
+ case 0x2: args << "asr"; break;
+ case 0x3:
+ if (imm5 == 0) {
+ args << "rrx";
+ } else {
+ args << "ror";
+ }
+ break;
+ }
+ if (shift_type != 0x3 /* rrx */) {
+ args << StringPrintf(" #%d", imm5);
+ }
+ }
+
+ } else if ((op2 & 0x40) == 0x40) { // 1xx xxxx
+ // Co-processor instructions
+ // |111|1|11|000000|0000|1111|1100|000|0 |0000|
+ // |5 3|2|10|987654|3 0|54 2|10 8|7 5|4 | 0|
+ // |---|-|--|------|----|----|----|---|---|----|
+ // |332|2|22|222222|1111|1111|1100|000|0 |0000|
+ // |1 9|8|76|543210|9 6|54 2|10 8|7 5|4 | 0|
+ // |---|-|--|------|----|----|----|---|---|----|
+ // |111| |11| op3 | Rn | |copr| |op4| |
+ uint32_t op3 = (instr >> 20) & 0x3F;
+ uint32_t coproc = (instr >> 8) & 0xF;
+ uint32_t op4 = (instr >> 4) & 0x1;
+ if ((op3 == 2 || op3 == 2 || op3 == 6 || op3 == 7) || // 00x1x
+ (op3 >= 8 && op3 <= 15) || (op3 >= 16 && op3 <= 31)) { // 001xxx, 01xxxx
+ // Extension register load/store instructions
+ // |111|1|110|00000|0000|1111|110|000000000|
+ // |5 3|2|109|87654|3 0|54 2|10 |87 54 0|
+ // |---|-|---|-----|----|----|---|---------|
+ // |332|2|222|22222|1111|1111|110|000000000|
+ // |1 9|8|765|43210|9 6|54 2|10 |87 54 0|
+ // |---|-|---|-----|----|----|---|---------|
+ // |111|T|110| op3 | Rn | |101| |
+ // 111 0 110 01001 0011 0000 101 000000011 - ec930a03
+ if (op3 == 9 || op3 == 0xD) { // VLDM
+ // 1110 110 PUDW1 nnnn dddd 101S iiii iiii
+ uint32_t P = (instr >> 24) & 1;
+ uint32_t U = (instr >> 23) & 1;
+ uint32_t D = (instr >> 22) & 1;
+ uint32_t W = (instr >> 21) & 1;
+ uint32_t S = (instr >> 8) & 1;
+ ArmRegister Rn(instr, 16);
+ uint32_t Vd = (instr >> 12) & 0xF;
+ uint32_t imm8 = instr & 0xFF;
+ uint32_t d = (S == 0 ? ((Vd << 1) | D) : (Vd | (D << 4)));
+ if (P == 0 && U == 0 && W == 0) {
+ // TODO: 64bit transfers between ARM core and extension registers.
+ } else if (P == 0 && U == 1 && Rn.r == 13) { // VPOP
+ opcode << "vpop" << (S == 0 ? ".f64" : ".f32");
+ args << d << " .. " << (d + imm8);
+ } else if (P == 1 && W == 0) { // VLDR
+ opcode << "vldr" << (S == 0 ? ".f64" : ".f32");
+ args << d << ", [" << Rn << ", #" << imm8 << "]";
+ } else { // VLDM
+ opcode << "vldm" << (S == 0 ? ".f64" : ".f32");
+ args << Rn << ", " << d << " .. " << (d + imm8);
+ }
+ }
+ } else if ((op3 & 0x30) == 0x20 && op4 == 0) { // 10 xxxx ... 0
+ if ((coproc & 0xE) == 0xA) {
+ // VFP data-processing instructions
+ // |111|1|1100|0000|0000|1111|110|0|00 |0|0|0000|
+ // |5 3|2|1098|7654|3 0|54 2|10 |8|76 |5|4|3 0|
+ // |---|-|----|----|----|----|---|-|----|-|-|----|
+ // |332|2|2222|2222|1111|1111|110|0|00 |0|0|0000|
+ // |1 9|8|7654|3210|9 6|54 2|109|8|76 |5|4|3 0|
+ // |---|-|----|----|----|----|---|-|----|-|-|----|
+ // |111|T|1110|opc1|opc2| |101| |opc3| | | |
+ // 111 0 1110|1111 0100 1110 101 0 01 1 0 1001 - eef4ea69
+ uint32_t opc1 = (instr >> 20) & 0xF;
+ uint32_t opc2 = (instr >> 16) & 0xF;
+ uint32_t opc3 = (instr >> 6) & 0x3;
+ if ((opc1 & 0xB) == 0xB) { // 1x11
+ // Other VFP data-processing instructions.
+ uint32_t D = (instr >> 22) & 0x1;
+ uint32_t Vd = (instr >> 12) & 0xF;
+ uint32_t sz = (instr >> 8) & 1;
+ uint32_t M = (instr >> 5) & 1;
+ uint32_t Vm = instr & 0xF;
+ bool dp_operation = sz == 1;
+ switch (opc2) {
+ case 0x1: // Vneg/Vsqrt
+ // 1110 11101 D 11 0001 dddd 101s o1M0 mmmm
+ opcode << (opc3 == 1 ? "vneg" : "vsqrt") << (dp_operation ? ".f64" : ".f32");
+ if (dp_operation) {
+ args << "f" << ((D << 4) | Vd) << ", " << "f" << ((M << 4) | Vm);
+ } else {
+ args << "f" << ((Vd << 1) | D) << ", " << "f" << ((Vm << 1) | M);
+ }
+ break;
+ case 0x4: case 0x5: { // Vector compare
+ // 1110 11101 D 11 0100 dddd 101 sE1M0 mmmm
+ opcode << (opc3 == 1 ? "vcmp" : "vcmpe") << (dp_operation ? ".f64" : ".f32");
+ if (dp_operation) {
+ args << "f" << ((D << 4) | Vd) << ", " << "f" << ((M << 4) | Vm);
+ } else {
+ args << "f" << ((Vd << 1) | D) << ", " << "f" << ((Vm << 1) | M);
+ }
+ break;
+ }
+ }
+ }
+ }
+ } else if ((op3 & 0x30) == 0x30) { // 11 xxxx
+ // Advanced SIMD
+ if ((instr & 0xFFBF0ED0) == 0xeeb10ac0) { // Vsqrt
+ // 1110 11101 D 11 0001 dddd 101S 11M0 mmmm
+ // 1110 11101 0 11 0001 1101 1011 1100 1000 - eeb1dbc8
+ uint32_t D = (instr >> 22) & 1;
+ uint32_t Vd = (instr >> 12) & 0xF;
+ uint32_t sz = (instr >> 8) & 1;
+ uint32_t M = (instr >> 5) & 1;
+ uint32_t Vm = instr & 0xF;
+ bool dp_operation = sz == 1;
+ opcode << "vsqrt" << (dp_operation ? ".f64" : ".f32");
+ if (dp_operation) {
+ args << "f" << ((D << 4) | Vd) << ", " << "f" << ((M << 4) | Vm);
+ } else {
+ args << "f" << ((Vd << 1) | D) << ", " << "f" << ((Vm << 1) | M);
+ }
+ }
+ }
+ }
+ break;
+ case 2:
+ if ((instr & 0x8000) == 0 && (op2 & 0x20) == 0) {
+ // Data-processing (modified immediate)
+ // |111|11|10|0000|0|0000|1|111|1100|00000000|
+ // |5 3|21|09|8765|4|3 0|5|4 2|10 8|7 5 0|
+ // |---|--|--|----|-|----|-|---|----|--------|
+ // |332|22|22|2222|2|1111|1|111|1100|00000000|
+ // |1 9|87|65|4321|0|9 6|5|4 2|10 8|7 5 0|
+ // |---|--|--|----|-|----|-|---|----|--------|
+ // |111|10|i0| op3|S| Rn |0|iii| Rd |iiiiiiii|
+ // 111 10 x0 xxxx x xxxx opxxx xxxx xxxxxxxx
+ uint32_t i = (instr >> 26) & 1;
+ uint32_t op3 = (instr >> 21) & 0xF;
+ uint32_t S = (instr >> 20) & 1;
+ ArmRegister Rn(instr, 16);
+ uint32_t imm3 = (instr >> 12) & 7;
+ ArmRegister Rd(instr, 8);
+ uint32_t imm8 = instr & 0xFF;
+ int32_t imm32 = (i << 11) | (imm3 << 8) | imm8;
+ if (Rn.r == 0xF && (op3 == 0x2 || op3 == 0x3)) {
+ if (op3 == 0x2) {
+ opcode << "mov";
+ if (S == 1) {
+ opcode << "s";
+ }
+ opcode << ".w";
+ } else {
+ opcode << "mvn";
+ if (S == 1) {
+ opcode << "s";
+ }
+ }
+ args << Rd << ", ThumbExpand(" << imm32 << ")";
+ } else if (Rd.r == 0xF && S == 1 &&
+ (op3 == 0x0 || op3 == 0x4 || op3 == 0x8 || op3 == 0xD)) {
+ if (op3 == 0x0) {
+ opcode << "tst";
+ } else if (op3 == 0x4) {
+ opcode << "teq";
+ } else if (op3 == 0x8) {
+ opcode << "cmw";
+ } else {
+ opcode << "cmp.w";
+ }
+ args << Rn << ", ThumbExpand(" << imm32 << ")";
+ } else {
+ switch (op3) {
+ case 0x0: opcode << "and"; break;
+ case 0x1: opcode << "bic"; break;
+ case 0x2: opcode << "orr"; break;
+ case 0x3: opcode << "orn"; break;
+ case 0x4: opcode << "eor"; break;
+ case 0x8: opcode << "add"; break;
+ case 0xA: opcode << "adc"; break;
+ case 0xB: opcode << "sbc"; break;
+ case 0xD: opcode << "sub"; break;
+ case 0xE: opcode << "rsb"; break;
+ default: opcode << "UNKNOWN DPMI-" << op3; break;
+ }
+ if (S == 1) {
+ opcode << "s";
+ }
+ args << Rd << ", " << Rn << ", ThumbExpand(" << imm32 << ")";
+ }
+ } else if ((instr & 0x8000) == 0 && (op2 & 0x20) != 0) {
+ // Data-processing (plain binary immediate)
+ // |111|11|10|00000|0000|1|111110000000000|
+ // |5 3|21|09|87654|3 0|5|4 0 5 0|
+ // |---|--|--|-----|----|-|---------------|
+ // |332|22|22|22222|1111|1|111110000000000|
+ // |1 9|87|65|43210|9 6|5|4 0 5 0|
+ // |---|--|--|-----|----|-|---------------|
+ // |111|10|x1| op3 | Rn |0|xxxxxxxxxxxxxxx|
+ uint32_t op3 = (instr >> 20) & 0x1F;
+ switch (op3) {
+ case 0x00: case 0x0A: {
+ // ADD/SUB.W Rd, Rn #imm12 - 111 10 i1 0101 0 nnnn 0 iii dddd iiiiiiii
+ ArmRegister Rd(instr, 8);
+ ArmRegister Rn(instr, 16);
+ uint32_t i = (instr >> 26) & 1;
+ uint32_t imm3 = (instr >> 12) & 0x7;
+ uint32_t imm8 = instr & 0xFF;
+ uint32_t imm12 = (i << 11) | (imm3 << 8) | imm8;
+ if (Rn.r != 0xF) {
+ opcode << (op3 == 0 ? "addw" : "subw");
+ args << Rd << ", " << Rn << ", #" << imm12;
+ } else {
+ opcode << "adr";
+ args << Rd << ", ";
+ DumpBranchTarget(args, instr_ptr + 4, (op3 == 0) ? imm12 : -imm12);
+ }
+ break;
+ }
+ case 0x04: case 0x0C: {
+ // MOVW/T Rd, #imm16 - 111 10 i0 0010 0 iiii 0 iii dddd iiiiiiii
+ ArmRegister Rd(instr, 8);
+ uint32_t i = (instr >> 26) & 1;
+ uint32_t imm3 = (instr >> 12) & 0x7;
+ uint32_t imm8 = instr & 0xFF;
+ uint32_t Rn = (instr >> 16) & 0xF;
+ uint32_t imm16 = (Rn << 12) | (i << 11) | (imm3 << 8) | imm8;
+ opcode << (op3 == 0x04 ? "movw" : "movt");
+ args << Rd << ", #" << imm16;
+ break;
+ }
+ case 0x16: {
+ // BFI Rd, Rn, #lsb, #width - 111 10 0 11 011 0 nnnn 0 iii dddd ii 0 iiiii
+ ArmRegister Rd(instr, 8);
+ ArmRegister Rn(instr, 16);
+ uint32_t msb = instr & 0x1F;
+ uint32_t imm2 = (instr >> 6) & 0x3;
+ uint32_t imm3 = (instr >> 12) & 0x7;
+ uint32_t lsb = (imm3 << 2) | imm2;
+ uint32_t width = msb - lsb + 1;
+ if (Rn.r != 0xF) {
+ opcode << "bfi";
+ args << Rd << ", " << Rn << ", #" << lsb << ", #" << width;
+ } else {
+ opcode << "bfc";
+ args << Rd << ", #" << lsb << ", #" << width;
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ } else {
+ // Branches and miscellaneous control
+ // |111|11|1000000|0000|1|111|1100|00000000|
+ // |5 3|21|0987654|3 0|5|4 2|10 8|7 5 0|
+ // |---|--|-------|----|-|---|----|--------|
+ // |332|22|2222222|1111|1|111|1100|00000000|
+ // |1 9|87|6543210|9 6|5|4 2|10 8|7 5 0|
+ // |---|--|-------|----|-|---|----|--------|
+ // |111|10| op2 | |1|op3|op4 | |
+
+ uint32_t op3 = (instr >> 12) & 7;
+ // uint32_t op4 = (instr >> 8) & 0xF;
+ switch (op3) {
+ case 0:
+ if ((op2 & 0x38) != 0x38) {
+ // Conditional branch
+ // |111|11|1|0000|000000|1|1|1 |1|1 |10000000000|
+ // |5 3|21|0|9876|543 0|5|4|3 |2|1 |0 5 0|
+ // |---|--|-|----|------|-|-|--|-|--|-----------|
+ // |332|22|2|2222|221111|1|1|1 |1|1 |10000000000|
+ // |1 9|87|6|5432|109 6|5|4|3 |2|1 |0 5 0|
+ // |---|--|-|----|------|-|-|--|-|--|-----------|
+ // |111|10|S|cond| imm6 |1|0|J1|0|J2| imm11 |
+ uint32_t S = (instr >> 26) & 1;
+ uint32_t J2 = (instr >> 11) & 1;
+ uint32_t J1 = (instr >> 13) & 1;
+ uint32_t imm6 = (instr >> 16) & 0x3F;
+ uint32_t imm11 = instr & 0x7FF;
+ uint32_t cond = (instr >> 22) & 0xF;
+ int32_t imm32 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1);
+ imm32 = (imm32 << 11) >> 11; // sign extend 21bit immediate
+ opcode << "b";
+ DumpCond(opcode, cond);
+ opcode << ".w";
+ DumpBranchTarget(args, instr_ptr + 4, imm32);
+ } else if (op2 == 0x3B) {
+ // Miscellaneous control instructions
+ uint32_t op5 = (instr >> 4) & 0xF;
+ switch (op5) {
+ case 4: opcode << "dsb"; break;
+ case 5: opcode << "dmb"; break;
+ case 6: opcode << "isb"; break;
+ }
+ }
+ break;
+ case 2:
+ if ((op2 & 0x38) == 0x38) {
+ if (op2 == 0x7F) {
+ opcode << "udf";
+ }
+ break;
+ }
+ // Else deliberate fall-through to B.
+ case 1: case 3: {
+ // B
+ // |111|11|1|0000|000000|11|1 |1|1 |10000000000|
+ // |5 3|21|0|9876|543 0|54|3 |2|1 |0 5 0|
+ // |---|--|-|----|------|--|--|-|--|-----------|
+ // |332|22|2|2222|221111|11|1 |1|1 |10000000000|
+ // |1 9|87|6|5 2|10 6|54|3 |2|1 |0 5 0|
+ // |---|--|-|----|------|--|--|-|--|-----------|
+ // |111|10|S|cond| imm6 |10|J1|0|J2| imm11 |
+ // |111|10|S| imm10 |10|J1|1|J2| imm11 |
+ uint32_t S = (instr >> 26) & 1;
+ uint32_t cond = (instr >> 22) & 0xF;
+ uint32_t J2 = (instr >> 11) & 1;
+ uint32_t form = (instr >> 12) & 1;
+ uint32_t J1 = (instr >> 13) & 1;
+ uint32_t imm10 = (instr >> 16) & 0x3FF;
+ uint32_t imm6 = (instr >> 16) & 0x3F;
+ uint32_t imm11 = instr & 0x7FF;
+ opcode << "b";
+ int32_t imm32;
+ if (form == 0) {
+ DumpCond(opcode, cond);
+ imm32 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1);
+ imm32 = (imm32 << 11) >> 11; // sign extend 21 bit immediate.
+ } else {
+ uint32_t I1 = ~(J1 ^ S);
+ uint32_t I2 = ~(J2 ^ S);
+ imm32 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
+ imm32 = (imm32 << 8) >> 8; // sign extend 24 bit immediate.
+ }
+ opcode << ".w";
+ DumpBranchTarget(args, instr_ptr + 4, imm32);
+ break;
+ }
+ case 4: case 6: case 5: case 7: {
+ // BL, BLX (immediate)
+ // |111|11|1|0000000000|11|1 |1|1 |10000000000|
+ // |5 3|21|0|9876543 0|54|3 |2|1 |0 5 0|
+ // |---|--|-|----------|--|--|-|--|-----------|
+ // |332|22|2|2222221111|11|1 |1|1 |10000000000|
+ // |1 9|87|6|5 0 6|54|3 |2|1 |0 5 0|
+ // |---|--|-|----------|--|--|-|--|-----------|
+ // |111|10|S| imm10 |11|J1|L|J2| imm11 |
+ uint32_t S = (instr >> 26) & 1;
+ uint32_t J2 = (instr >> 11) & 1;
+ uint32_t L = (instr >> 12) & 1;
+ uint32_t J1 = (instr >> 13) & 1;
+ uint32_t imm10 = (instr >> 16) & 0x3FF;
+ uint32_t imm11 = instr & 0x7FF;
+ if (L == 0) {
+ opcode << "bx";
+ } else {
+ opcode << "blx";
+ }
+ uint32_t I1 = ~(J1 ^ S);
+ uint32_t I2 = ~(J2 ^ S);
+ int32_t imm32 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
+ imm32 = (imm32 << 8) >> 8; // sign extend 24 bit immediate.
+ DumpBranchTarget(args, instr_ptr + 4, imm32);
+ break;
+ }
+ }
+ }
+ break;
+ case 3:
+ switch (op2) {
+ case 0x00: case 0x02: case 0x04: case 0x06: // 000xxx0
+ case 0x08: case 0x0A: case 0x0C: case 0x0E: {
+ // Store single data item
+ // |111|11|100|000|0|0000|1111|110000|000000|
+ // |5 3|21|098|765|4|3 0|5 2|10 6|5 0|
+ // |---|--|---|---|-|----|----|------|------|
+ // |332|22|222|222|2|1111|1111|110000|000000|
+ // |1 9|87|654|321|0|9 6|5 2|10 6|5 0|
+ // |---|--|---|---|-|----|----|------|------|
+ // |111|11|000|op3|0| | | op4 | |
+ uint32_t op3 = (instr >> 21) & 7;
+ // uint32_t op4 = (instr >> 6) & 0x3F;
+ switch (op3) {
+ case 0x0: case 0x4: {
+ // STRB Rt,[Rn,#+/-imm8] - 111 11 00 0 0 00 0 nnnn tttt 1 PUWii ii iiii
+ // STRB Rt,[Rn,Rm,lsl #imm2] - 111 11 00 0 0 00 0 nnnn tttt 0 00000 ii mmmm
+ ArmRegister Rn(instr, 16);
+ ArmRegister Rt(instr, 12);
+ opcode << "strb";
+ if ((instr & 0x800) != 0) {
+ uint32_t imm8 = instr & 0xFF;
+ args << Rt << ", [" << Rn << ",#" << imm8 << "]";
+ } else {
+ uint32_t imm2 = (instr >> 4) & 3;
+ ArmRegister Rm(instr, 0);
+ args << Rt << ", [" << Rn << ", " << Rm;
+ if (imm2 != 0) {
+ args << ", " << "lsl #" << imm2;
+ }
+ args << "]";
+ }
+ break;
+ }
+ case 0x2: case 0x6: {
+ ArmRegister Rn(instr, 16);
+ ArmRegister Rt(instr, 12);
+ if (op3 == 2) {
+ if ((instr & 0x800) != 0) {
+ // STR Rt, [Rn, #imm8] - 111 11 000 010 0 nnnn tttt 1PUWiiiiiiii
+ uint32_t P = (instr >> 10) & 1;
+ uint32_t U = (instr >> 9) & 1;
+ uint32_t W = (instr >> 8) & 1;
+ uint32_t imm8 = instr & 0xFF;
+ int32_t imm32 = (imm8 << 24) >> 24; // sign-extend imm8
+ if (Rn.r == 13 && P == 1 && U == 0 && W == 1 && imm32 == 4) {
+ opcode << "push";
+ args << Rt;
+ } else if (Rn.r == 15 || (P == 0 && W == 0)) {
+ opcode << "UNDEFINED";
+ } else {
+ if (P == 1 && U == 1 && W == 0) {
+ opcode << "strt";
+ } else {
+ opcode << "str";
+ }
+ args << Rt << ", [" << Rn;
+ if (P == 0 && W == 1) {
+ args << "], #" << imm32;
+ } else {
+ args << ", #" << imm32 << "]";
+ if (W == 1) {
+ args << "!";
+ }
+ }
+ }
+ } else {
+ // STR Rt, [Rn, Rm, LSL #imm2] - 111 11 000 010 0 nnnn tttt 000000iimmmm
+ ArmRegister Rn(instr, 16);
+ ArmRegister Rt(instr, 12);
+ ArmRegister Rm(instr, 0);
+ uint32_t imm2 = (instr >> 4) & 3;
+ opcode << "str.w";
+ args << Rt << ", [" << Rn << ", " << Rm;
+ if (imm2 != 0) {
+ args << ", lsl #" << imm2;
+ }
+ args << "]";
+ }
+ } else if (op3 == 6) {
+ // STR.W Rt, [Rn, #imm12] - 111 11 000 110 0 nnnn tttt iiiiiiiiiiii
+ uint32_t imm12 = instr & 0xFFF;
+ opcode << "str.w";
+ args << Rt << ", [" << Rn << ", #" << imm12 << "]";
+ }
+ break;
+ }
+ }
+
+ break;
+ }
+ case 0x03: case 0x0B: case 0x13: case 0x1B: { // 00xx011
+ // Load halfword
+ // |111|11|10|0 0|00|0|0000|1111|110000|000000|
+ // |5 3|21|09|8 7|65|4|3 0|5 2|10 6|5 0|
+ // |---|--|--|---|--|-|----|----|------|------|
+ // |332|22|22|2 2|22|2|1111|1111|110000|000000|
+ // |1 9|87|65|4 3|21|0|9 6|5 2|10 6|5 0|
+ // |---|--|--|---|--|-|----|----|------|------|
+ // |111|11|00|op3|01|1| Rn | Rt | op4 | |
+ // |111|11| op2 | | | imm12 |
+ uint32_t op3 = (instr >> 23) & 3;
+ ArmRegister Rn(instr, 16);
+ ArmRegister Rt(instr, 12);
+ if (Rt.r != 15) {
+ if (op3 == 1) {
+ // LDRH.W Rt, [Rn, #imm12] - 111 11 00 01 011 nnnn tttt iiiiiiiiiiii
+ uint32_t imm12 = instr & 0xFFF;
+ opcode << "ldrh.w";
+ args << Rt << ", [" << Rn << ", #" << imm12 << "]";
+ if (Rn.r == 9) {
+ args << " ; ";
+ Thread::DumpThreadOffset(args, imm12, 4);
+ } else if (Rn.r == 15) {
+ intptr_t lit_adr = reinterpret_cast<intptr_t>(instr_ptr);
+ lit_adr = RoundDown(lit_adr, 4) + 4 + imm12;
+ args << " ; " << reinterpret_cast<void*>(*reinterpret_cast<int32_t*>(lit_adr));
+ }
+ } else if (op3 == 3) {
+ // LDRSH.W Rt, [Rn, #imm12] - 111 11 00 11 011 nnnn tttt iiiiiiiiiiii
+ uint32_t imm12 = instr & 0xFFF;
+ opcode << "ldrsh.w";
+ args << Rt << ", [" << Rn << ", #" << imm12 << "]";
+ if (Rn.r == 9) {
+ args << " ; ";
+ Thread::DumpThreadOffset(args, imm12, 4);
+ } else if (Rn.r == 15) {
+ intptr_t lit_adr = reinterpret_cast<intptr_t>(instr_ptr);
+ lit_adr = RoundDown(lit_adr, 4) + 4 + imm12;
+ args << " ; " << reinterpret_cast<void*>(*reinterpret_cast<int32_t*>(lit_adr));
+ }
+ }
+ }
+ break;
+ }
+ case 0x05: case 0x0D: case 0x15: case 0x1D: { // 00xx101
+ // Load word
+ // |111|11|10|0 0|00|0|0000|1111|110000|000000|
+ // |5 3|21|09|8 7|65|4|3 0|5 2|10 6|5 0|
+ // |---|--|--|---|--|-|----|----|------|------|
+ // |332|22|22|2 2|22|2|1111|1111|110000|000000|
+ // |1 9|87|65|4 3|21|0|9 6|5 2|10 6|5 0|
+ // |---|--|--|---|--|-|----|----|------|------|
+ // |111|11|00|op3|10|1| Rn | Rt | op4 | |
+ // |111|11| op2 | | | imm12 |
+ uint32_t op3 = (instr >> 23) & 3;
+ uint32_t op4 = (instr >> 6) & 0x3F;
+ ArmRegister Rn(instr, 16);
+ ArmRegister Rt(instr, 12);
+ if (op3 == 1 || Rn.r == 15) {
+ // LDR.W Rt, [Rn, #imm12] - 111 11 00 00 101 nnnn tttt iiiiiiiiiiii
+ // LDR.W Rt, [PC, #imm12] - 111 11 00 0x 101 1111 tttt iiiiiiiiiiii
+ uint32_t imm12 = instr & 0xFFF;
+ opcode << "ldr.w";
+ args << Rt << ", [" << Rn << ", #" << imm12 << "]";
+ if (Rn.r == 9) {
+ args << " ; ";
+ Thread::DumpThreadOffset(args, imm12, 4);
+ } else if (Rn.r == 15) {
+ intptr_t lit_adr = reinterpret_cast<intptr_t>(instr_ptr);
+ lit_adr = RoundDown(lit_adr, 4) + 4 + imm12;
+ args << " ; " << reinterpret_cast<void*>(*reinterpret_cast<int32_t*>(lit_adr));
+ }
+ } else if (op4 == 0) {
+ // LDR.W Rt, [Rn, Rm{, LSL #imm2}] - 111 11 00 00 101 nnnn tttt 000000iimmmm
+ uint32_t imm2 = (instr >> 4) & 0xF;
+ ArmRegister rm(instr, 0);
+ opcode << "ldr.w";
+ args << Rt << ", [" << Rn << ", " << rm;
+ if (imm2 != 0) {
+ args << ", lsl #" << imm2;
+ }
+ args << "]";
+ } else {
+ // LDRT Rt, [Rn, #imm8] - 111 11 00 00 101 nnnn tttt 1110iiiiiiii
+ uint32_t imm8 = instr & 0xFF;
+ opcode << "ldrt";
+ args << Rt << ", [" << Rn << ", #" << imm8 << "]";
+ }
+ break;
+ }
+ }
+ default:
+ break;
+ }
+
+ // Apply any IT-block conditions to the opcode if necessary.
+ if (!it_conditions_.empty()) {
+ opcode << it_conditions_.back();
+ it_conditions_.pop_back();
+ }
+
+ os << StringPrintf("%p: %08x\t%-7s ", instr_ptr, instr, opcode.str().c_str()) << args.str() << '\n';
+ return 4;
+} // NOLINT(readability/fn_size)
+
+size_t DisassemblerArm::DumpThumb16(std::ostream& os, const uint8_t* instr_ptr) {
+ uint16_t instr = ReadU16(instr_ptr);
+ bool is_32bit = ((instr & 0xF000) == 0xF000) || ((instr & 0xF800) == 0xE800);
+ if (is_32bit) {
+ return DumpThumb32(os, instr_ptr);
+ } else {
+ std::ostringstream opcode;
+ std::ostringstream args;
+ uint16_t opcode1 = instr >> 10;
+ if (opcode1 < 0x10) {
+ // shift (immediate), add, subtract, move, and compare
+ uint16_t opcode2 = instr >> 9;
+ switch (opcode2) {
+ case 0x0: case 0x1: case 0x2: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
+ case 0x8: case 0x9: case 0xA: case 0xB: {
+ // Logical shift left - 00 000xx iii mmm ddd
+ // Logical shift right - 00 001xx iii mmm ddd
+ // Arithmetic shift right - 00 010xx iii mmm ddd
+ uint16_t imm5 = (instr >> 6) & 0x1F;
+ ThumbRegister rm(instr, 3);
+ ThumbRegister Rd(instr, 0);
+ if (opcode2 <= 3) {
+ opcode << "lsls";
+ } else if (opcode2 <= 7) {
+ opcode << "lsrs";
+ } else {
+ opcode << "asrs";
+ }
+ args << Rd << ", " << rm << ", #" << imm5;
+ break;
+ }
+ case 0xC: case 0xD: case 0xE: case 0xF: {
+ // Add register - 00 01100 mmm nnn ddd
+ // Sub register - 00 01101 mmm nnn ddd
+ // Add 3-bit immediate - 00 01110 iii nnn ddd
+ // Sub 3-bit immediate - 00 01111 iii nnn ddd
+ uint16_t imm3_or_Rm = (instr >> 6) & 7;
+ ThumbRegister Rn(instr, 3);
+ ThumbRegister Rd(instr, 0);
+ if ((opcode2 & 2) != 0 && imm3_or_Rm == 0) {
+ opcode << "mov";
+ } else {
+ if ((opcode2 & 1) == 0) {
+ opcode << "adds";
+ } else {
+ opcode << "subs";
+ }
+ }
+ args << Rd << ", " << Rn;
+ if ((opcode2 & 2) == 0) {
+ ArmRegister Rm(imm3_or_Rm);
+ args << ", " << Rm;
+ } else if (imm3_or_Rm != 0) {
+ args << ", #" << imm3_or_Rm;
+ }
+ break;
+ }
+ case 0x10: case 0x11: case 0x12: case 0x13:
+ case 0x14: case 0x15: case 0x16: case 0x17:
+ case 0x18: case 0x19: case 0x1A: case 0x1B:
+ case 0x1C: case 0x1D: case 0x1E: case 0x1F: {
+ // MOVS Rd, #imm8 - 00100 ddd iiiiiiii
+ // CMP Rn, #imm8 - 00101 nnn iiiiiiii
+ // ADDS Rn, #imm8 - 00110 nnn iiiiiiii
+ // SUBS Rn, #imm8 - 00111 nnn iiiiiiii
+ ThumbRegister Rn(instr, 8);
+ uint16_t imm8 = instr & 0xFF;
+ switch (opcode2 >> 2) {
+ case 4: opcode << "movs"; break;
+ case 5: opcode << "cmp"; break;
+ case 6: opcode << "adds"; break;
+ case 7: opcode << "subs"; break;
+ }
+ args << Rn << ", #" << imm8;
+ break;
+ }
+ default:
+ break;
+ }
+ } else if (opcode1 == 0x10) {
+ // Data-processing
+ uint16_t opcode2 = (instr >> 6) & 0xF;
+ ThumbRegister rm(instr, 3);
+ ThumbRegister rdn(instr, 0);
+ opcode << kThumbDataProcessingOperations[opcode2];
+ args << rdn << ", " << rm;
+ } else if (opcode1 == 0x11) {
+ // Special data instructions and branch and exchange
+ uint16_t opcode2 = (instr >> 6) & 0x0F;
+ switch (opcode2) {
+ case 0x0: case 0x1: case 0x2: case 0x3: {
+ // Add low registers - 010001 0000 xxxxxx
+ // Add high registers - 010001 0001/001x xxxxxx
+ uint16_t DN = (instr >> 7) & 1;
+ ArmRegister rm(instr, 3);
+ uint16_t Rdn = instr & 7;
+ ArmRegister DN_Rdn((DN << 3) | Rdn);
+ opcode << "add";
+ args << DN_Rdn << ", " << rm;
+ break;
+ }
+ case 0x8: case 0x9: case 0xA: case 0xB: {
+ // Move low registers - 010001 1000 xxxxxx
+ // Move high registers - 010001 1001/101x xxxxxx
+ uint16_t DN = (instr >> 7) & 1;
+ ArmRegister rm(instr, 3);
+ uint16_t Rdn = instr & 7;
+ ArmRegister DN_Rdn((DN << 3) | Rdn);
+ opcode << "mov";
+ args << DN_Rdn << ", " << rm;
+ break;
+ }
+ case 0x5: case 0x6: case 0x7: {
+ // Compare high registers - 010001 0101/011x xxxxxx
+ uint16_t N = (instr >> 7) & 1;
+ ArmRegister rm(instr, 3);
+ uint16_t Rn = instr & 7;
+ ArmRegister N_Rn((N << 3) | Rn);
+ opcode << "cmp";
+ args << N_Rn << ", " << rm;
+ break;
+ }
+ case 0xC: case 0xD: case 0xE: case 0xF: {
+ // Branch and exchange - 010001 110x xxxxxx
+ // Branch with link and exchange - 010001 111x xxxxxx
+ ArmRegister rm(instr, 3);
+ opcode << ((opcode2 & 0x2) == 0 ? "bx" : "blx");
+ args << rm;
+ break;
+ }
+ default:
+ break;
+ }
+ } else if (opcode1 == 0x12 || opcode1 == 0x13) { // 01001x
+ ThumbRegister Rt(instr, 8);
+ uint16_t imm8 = instr & 0xFF;
+ opcode << "ldr";
+ args << Rt << ", [pc, #" << (imm8 << 2) << "]";
+ } else if ((opcode1 >= 0x14 && opcode1 <= 0x17) || // 0101xx
+ (opcode1 >= 0x18 && opcode1 <= 0x1f) || // 011xxx
+ (opcode1 >= 0x20 && opcode1 <= 0x27)) { // 100xxx
+ // Load/store single data item
+ uint16_t opA = (instr >> 12) & 0xF;
+ if (opA == 0x5) {
+ uint16_t opB = (instr >> 9) & 0x7;
+ ThumbRegister Rm(instr, 6);
+ ThumbRegister Rn(instr, 3);
+ ThumbRegister Rt(instr, 0);
+ switch (opB) {
+ case 0: opcode << "str"; break;
+ case 1: opcode << "strh"; break;
+ case 2: opcode << "strb"; break;
+ case 3: opcode << "ldrsb"; break;
+ case 4: opcode << "ldr"; break;
+ case 5: opcode << "ldrh"; break;
+ case 6: opcode << "ldrb"; break;
+ case 7: opcode << "ldrsh"; break;
+ }
+ args << Rt << ", [" << Rn << ", " << Rm << "]";
+ } else if (opA == 9) {
+ uint16_t opB = (instr >> 11) & 1;
+ ThumbRegister Rt(instr, 8);
+ uint16_t imm8 = instr & 0xFF;
+ opcode << (opB == 0 ? "str" : "ldr");
+ args << Rt << ", [sp, #" << (imm8 << 2) << "]";
+ } else {
+ uint16_t imm5 = (instr >> 6) & 0x1F;
+ uint16_t opB = (instr >> 11) & 1;
+ ThumbRegister Rn(instr, 3);
+ ThumbRegister Rt(instr, 0);
+ switch (opA) {
+ case 6:
+ imm5 <<= 2;
+ opcode << (opB == 0 ? "str" : "ldr");
+ break;
+ case 7:
+ imm5 <<= 0;
+ opcode << (opB == 0 ? "strb" : "ldrb");
+ break;
+ case 8:
+ imm5 <<= 1;
+ opcode << (opB == 0 ? "strh" : "ldrh");
+ break;
+ }
+ args << Rt << ", [" << Rn << ", #" << imm5 << "]";
+ }
+ } else if (opcode1 >= 0x34 && opcode1 <= 0x37) { // 1101xx
+ int8_t imm8 = instr & 0xFF;
+ uint32_t cond = (instr >> 8) & 0xF;
+ opcode << "b";
+ DumpCond(opcode, cond);
+ DumpBranchTarget(args, instr_ptr + 4, (imm8 << 1));
+ } else if ((instr & 0xF800) == 0xA800) {
+ // Generate SP-relative address
+ ThumbRegister rd(instr, 8);
+ int imm8 = instr & 0xFF;
+ opcode << "add";
+ args << rd << ", sp, #" << (imm8 << 2);
+ } else if ((instr & 0xF000) == 0xB000) {
+ // Miscellaneous 16-bit instructions
+ uint16_t opcode2 = (instr >> 5) & 0x7F;
+ switch (opcode2) {
+ case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: {
+ // Add immediate to SP - 1011 00000 ii iiiii
+ // Subtract immediate from SP - 1011 00001 ii iiiii
+ int imm7 = instr & 0x7F;
+ opcode << ((opcode2 & 4) == 0 ? "add" : "sub");
+ args << "sp, sp, #" << (imm7 << 2);
+ break;
+ }
+ case 0x08: case 0x09: case 0x0A: case 0x0B: // 0001xxx
+ case 0x0C: case 0x0D: case 0x0E: case 0x0F:
+ case 0x18: case 0x19: case 0x1A: case 0x1B: // 0011xxx
+ case 0x1C: case 0x1D: case 0x1E: case 0x1F:
+ case 0x48: case 0x49: case 0x4A: case 0x4B: // 1001xxx
+ case 0x4C: case 0x4D: case 0x4E: case 0x4F:
+ case 0x58: case 0x59: case 0x5A: case 0x5B: // 1011xxx
+ case 0x5C: case 0x5D: case 0x5E: case 0x5F: {
+ // CBNZ, CBZ
+ uint16_t op = (instr >> 11) & 1;
+ uint16_t i = (instr >> 9) & 1;
+ uint16_t imm5 = (instr >> 3) & 0x1F;
+ ThumbRegister Rn(instr, 0);
+ opcode << (op != 0 ? "cbnz" : "cbz");
+ uint32_t imm32 = (i << 6) | (imm5 << 1);
+ args << Rn << ", ";
+ DumpBranchTarget(args, instr_ptr + 4, imm32);
+ break;
+ }
+ case 0x78: case 0x79: case 0x7A: case 0x7B: // 1111xxx
+ case 0x7C: case 0x7D: case 0x7E: case 0x7F: {
+ // If-Then, and hints
+ uint16_t opA = (instr >> 4) & 0xF;
+ uint16_t opB = instr & 0xF;
+ if (opB == 0) {
+ switch (opA) {
+ case 0: opcode << "nop"; break;
+ case 1: opcode << "yield"; break;
+ case 2: opcode << "wfe"; break;
+ case 3: opcode << "sev"; break;
+ default: break;
+ }
+ } else {
+ uint32_t first_cond = opA;
+ uint32_t mask = opB;
+ opcode << "it";
+
+ // Flesh out the base "it" opcode with the specific collection of 't's and 'e's,
+ // and store up the actual condition codes we'll want to add to the next few opcodes.
+ size_t count = 3 - CTZ(mask);
+ it_conditions_.resize(count + 2); // Plus the implicit 't', plus the "" for the IT itself.
+ for (size_t i = 0; i < count; ++i) {
+ bool positive_cond = ((first_cond & 1) != 0);
+ bool positive_mask = ((mask & (1 << (3 - i))) != 0);
+ if (positive_mask == positive_cond) {
+ opcode << 't';
+ it_conditions_[i] = kConditionCodeNames[first_cond];
+ } else {
+ opcode << 'e';
+ it_conditions_[i] = kConditionCodeNames[first_cond ^ 1];
+ }
+ }
+ it_conditions_[count] = kConditionCodeNames[first_cond]; // The implicit 't'.
+
+ it_conditions_[count + 1] = ""; // No condition code for the IT itself...
+ DumpCond(args, first_cond); // ...because it's considered an argument.
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ } else if (((instr & 0xF000) == 0x5000) || ((instr & 0xE000) == 0x6000) ||
+ ((instr & 0xE000) == 0x8000)) {
+ // Load/store single data item
+ uint16_t opA = instr >> 12;
+ // uint16_t opB = (instr >> 9) & 7;
+ switch (opA) {
+ case 0x6: {
+ // STR Rt, [Rn, #imm] - 01100 iiiii nnn ttt
+ // LDR Rt, [Rn, #imm] - 01101 iiiii nnn ttt
+ uint16_t imm5 = (instr >> 6) & 0x1F;
+ ThumbRegister Rn(instr, 3);
+ ThumbRegister Rt(instr, 0);
+ opcode << ((instr & 0x800) == 0 ? "str" : "ldr");
+ args << Rt << ", [" << Rn << ", #" << (imm5 << 2) << "]";
+ break;
+ }
+ case 0x9: {
+ // STR Rt, [SP, #imm] - 01100 ttt iiiiiiii
+ // LDR Rt, [SP, #imm] - 01101 ttt iiiiiiii
+ uint16_t imm8 = instr & 0xFF;
+ ThumbRegister Rt(instr, 8);
+ opcode << ((instr & 0x800) == 0 ? "str" : "ldr");
+ args << Rt << ", [sp, #" << (imm8 << 2) << "]";
+ break;
+ }
+ default:
+ break;
+ }
+ } else if (opcode1 == 0x38 || opcode1 == 0x39) {
+ uint16_t imm11 = instr & 0x7FFF;
+ int32_t imm32 = imm11 << 1;
+ imm32 = (imm32 << 20) >> 20; // sign extend 12 bit immediate
+ opcode << "b";
+ DumpBranchTarget(args, instr_ptr + 4, imm32);
+ }
+
+ // Apply any IT-block conditions to the opcode if necessary.
+ if (!it_conditions_.empty()) {
+ opcode << it_conditions_.back();
+ it_conditions_.pop_back();
+ }
+
+ os << StringPrintf("%p: %04x \t%-7s ", instr_ptr, instr, opcode.str().c_str()) << args.str() << '\n';
+ }
+ return 2;
+}
+
+} // namespace arm
+} // namespace art
diff --git a/disassembler/disassembler_arm.h b/disassembler/disassembler_arm.h
new file mode 100644
index 0000000..2e699ff
--- /dev/null
+++ b/disassembler/disassembler_arm.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ART_DISASSEMBLER_DISASSEMBLER_ARM_H_
+#define ART_DISASSEMBLER_DISASSEMBLER_ARM_H_
+
+#include <vector>
+
+#include "disassembler.h"
+
+namespace art {
+namespace arm {
+
+class DisassemblerArm : public Disassembler {
+ public:
+ DisassemblerArm();
+
+ virtual size_t Dump(std::ostream& os, const uint8_t* begin);
+ virtual void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end);
+ private:
+ void DumpArm(std::ostream& os, const uint8_t* instr);
+
+ // Returns the size of the instruction just decoded
+ size_t DumpThumb16(std::ostream& os, const uint8_t* instr);
+ size_t DumpThumb32(std::ostream& os, const uint8_t* instr_ptr);
+
+ void DumpBranchTarget(std::ostream& os, const uint8_t* instr_ptr, int32_t imm32);
+ void DumpCond(std::ostream& os, uint32_t cond);
+
+ std::vector<const char*> it_conditions_;
+
+ DISALLOW_COPY_AND_ASSIGN(DisassemblerArm);
+};
+
+} // namespace arm
+} // namespace art
+
+#endif // ART_DISASSEMBLER_DISASSEMBLER_ARM_H_
diff --git a/disassembler/disassembler_mips.cc b/disassembler/disassembler_mips.cc
new file mode 100644
index 0000000..25bbae6
--- /dev/null
+++ b/disassembler/disassembler_mips.cc
@@ -0,0 +1,275 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "disassembler_mips.h"
+
+#include <iostream>
+
+#include "base/logging.h"
+#include "base/stringprintf.h"
+#include "thread.h"
+
+namespace art {
+namespace mips {
+
+struct MipsInstruction {
+ uint32_t mask;
+ uint32_t value;
+ const char* name;
+ const char* args_fmt;
+
+ bool Matches(uint32_t instruction) const {
+ return (instruction & mask) == value;
+ }
+};
+
+static const uint32_t kOpcodeShift = 26;
+
+static const uint32_t kCop1 = (17 << kOpcodeShift);
+
+static const uint32_t kITypeMask = (0x3f << kOpcodeShift);
+static const uint32_t kJTypeMask = (0x3f << kOpcodeShift);
+static const uint32_t kRTypeMask = ((0x3f << kOpcodeShift) | (0x3f));
+static const uint32_t kSpecial2Mask = (0x3f << kOpcodeShift);
+static const uint32_t kFpMask = kRTypeMask;
+
+static const MipsInstruction gMipsInstructions[] = {
+ // "sll r0, r0, 0" is the canonical "nop", used in delay slots.
+ { 0xffffffff, 0, "nop", "" },
+
+ // R-type instructions.
+ { kRTypeMask, 0, "sll", "DTA", },
+ // 0, 1, movci
+ { kRTypeMask, 2, "srl", "DTA", },
+ { kRTypeMask, 3, "sra", "DTA", },
+ { kRTypeMask, 4, "sllv", "DTS", },
+ { kRTypeMask, 6, "srlv", "DTS", },
+ { kRTypeMask, 7, "srav", "DTS", },
+ { kRTypeMask, 8, "jr", "S", },
+ { kRTypeMask | (0x1f << 11), 9 | (31 << 11), "jalr", "S", }, // rd = 31 is implicit.
+ { kRTypeMask, 9, "jalr", "DS", }, // General case.
+ { kRTypeMask | (0x1f << 6), 10, "movz", "DST", },
+ { kRTypeMask | (0x1f << 6), 11, "movn", "DST", },
+ { kRTypeMask, 12, "syscall", "", }, // TODO: code
+ { kRTypeMask, 13, "break", "", }, // TODO: code
+ { kRTypeMask, 15, "sync", "", }, // TODO: type
+ { kRTypeMask, 16, "mfhi", "D", },
+ { kRTypeMask, 17, "mthi", "S", },
+ { kRTypeMask, 18, "mflo", "D", },
+ { kRTypeMask, 19, "mtlo", "S", },
+ { kRTypeMask, 24, "mult", "ST", },
+ { kRTypeMask, 25, "multu", "ST", },
+ { kRTypeMask, 26, "div", "ST", },
+ { kRTypeMask, 27, "divu", "ST", },
+ { kRTypeMask, 32, "add", "DST", },
+ { kRTypeMask, 33, "addu", "DST", },
+ { kRTypeMask, 34, "sub", "DST", },
+ { kRTypeMask, 35, "subu", "DST", },
+ { kRTypeMask, 36, "and", "DST", },
+ { kRTypeMask, 37, "or", "DST", },
+ { kRTypeMask, 38, "xor", "DST", },
+ { kRTypeMask, 39, "nor", "DST", },
+ { kRTypeMask, 42, "slt", "DST", },
+ { kRTypeMask, 43, "sltu", "DST", },
+ // 0, 48, tge
+ // 0, 49, tgeu
+ // 0, 50, tlt
+ // 0, 51, tltu
+ // 0, 52, teq
+ // 0, 54, tne
+
+ // SPECIAL2
+ { kSpecial2Mask | 0x7ff, (28 << kOpcodeShift) | 2, "mul", "DST" },
+ { kSpecial2Mask | 0x7ff, (28 << kOpcodeShift) | 32, "clz", "DS" },
+ { kSpecial2Mask | 0xffff, (28 << kOpcodeShift) | 0, "madd", "ST" },
+ { kSpecial2Mask | 0xffff, (28 << kOpcodeShift) | 1, "maddu", "ST" },
+ { kSpecial2Mask | 0xffff, (28 << kOpcodeShift) | 2, "mul", "DST" },
+ { kSpecial2Mask | 0xffff, (28 << kOpcodeShift) | 4, "msub", "ST" },
+ { kSpecial2Mask | 0xffff, (28 << kOpcodeShift) | 5, "msubu", "ST" },
+ { kSpecial2Mask | 0x3f, (28 << kOpcodeShift) | 0x3f, "sdbbp", "" }, // TODO: code
+
+ // J-type instructions.
+ { kJTypeMask, 2 << kOpcodeShift, "j", "L" },
+ { kJTypeMask, 3 << kOpcodeShift, "jal", "L" },
+
+ // I-type instructions.
+ { kITypeMask, 4 << kOpcodeShift, "beq", "STB" },
+ { kITypeMask, 5 << kOpcodeShift, "bne", "STB" },
+ { kITypeMask | (0x1f << 16), 1 << kOpcodeShift | (1 << 16), "bgez", "SB" },
+ { kITypeMask | (0x1f << 16), 1 << kOpcodeShift | (0 << 16), "bltz", "SB" },
+ { kITypeMask | (0x1f << 16), 1 << kOpcodeShift | (2 << 16), "bltzl", "SB" },
+ { kITypeMask | (0x1f << 16), 1 << kOpcodeShift | (16 << 16), "bltzal", "SB" },
+ { kITypeMask | (0x1f << 16), 1 << kOpcodeShift | (18 << 16), "bltzall", "SB" },
+ { kITypeMask | (0x1f << 16), 6 << kOpcodeShift | (0 << 16), "blez", "SB" },
+ { kITypeMask | (0x1f << 16), 7 << kOpcodeShift | (0 << 16), "bgtz", "SB" },
+
+ { 0xffff0000, (4 << kOpcodeShift), "b", "B" },
+ { 0xffff0000, (1 << kOpcodeShift) | (17 << 16), "bal", "B" },
+
+ { kITypeMask, 8 << kOpcodeShift, "addi", "TSi", },
+ { kITypeMask, 9 << kOpcodeShift, "addiu", "TSi", },
+ { kITypeMask, 10 << kOpcodeShift, "slti", "TSi", },
+ { kITypeMask, 11 << kOpcodeShift, "sltiu", "TSi", },
+ { kITypeMask, 12 << kOpcodeShift, "andi", "TSi", },
+ { kITypeMask, 13 << kOpcodeShift, "ori", "TSi", },
+ { kITypeMask, 14 << kOpcodeShift, "ori", "TSi", },
+ { kITypeMask, 15 << kOpcodeShift, "lui", "TI", },
+
+ { kITypeMask, 32u << kOpcodeShift, "lb", "TO", },
+ { kITypeMask, 33u << kOpcodeShift, "lh", "TO", },
+ { kITypeMask, 35u << kOpcodeShift, "lw", "TO", },
+ { kITypeMask, 36u << kOpcodeShift, "lbu", "TO", },
+ { kITypeMask, 37u << kOpcodeShift, "lhu", "TO", },
+ { kITypeMask, 40u << kOpcodeShift, "sb", "TO", },
+ { kITypeMask, 41u << kOpcodeShift, "sh", "TO", },
+ { kITypeMask, 43u << kOpcodeShift, "sw", "TO", },
+ { kITypeMask, 49u << kOpcodeShift, "lwc1", "tO", },
+ { kITypeMask, 57u << kOpcodeShift, "swc1", "tO", },
+
+ // Floating point.
+ { kFpMask, kCop1 | 0, "add", "fdst" },
+ { kFpMask, kCop1 | 1, "sub", "fdst" },
+ { kFpMask, kCop1 | 2, "mul", "fdst" },
+ { kFpMask, kCop1 | 3, "div", "fdst" },
+ { kFpMask | (0x1f << 16), kCop1 | 4, "sqrt", "fdst" },
+ { kFpMask | (0x1f << 16), kCop1 | 5, "abs", "fds" },
+ { kFpMask | (0x1f << 16), kCop1 | 6, "mov", "fds" },
+ { kFpMask | (0x1f << 16), kCop1 | 7, "neg", "fds" },
+ { kFpMask | (0x1f << 16), kCop1 | 8, "round.l", "fds" },
+ { kFpMask | (0x1f << 16), kCop1 | 9, "trunc.l", "fds" },
+ { kFpMask | (0x1f << 16), kCop1 | 10, "ceil.l", "fds" },
+ { kFpMask | (0x1f << 16), kCop1 | 11, "floor.l", "fds" },
+ { kFpMask | (0x1f << 16), kCop1 | 12, "round.w", "fds" },
+ { kFpMask | (0x1f << 16), kCop1 | 13, "trunc.w", "fds" },
+ { kFpMask | (0x1f << 16), kCop1 | 14, "ceil.w", "fds" },
+ { kFpMask | (0x1f << 16), kCop1 | 15, "floor.w", "fds" },
+ { kFpMask | (0x1f << 16), kCop1 | 32, "cvt.s", "fds" },
+ { kFpMask | (0x1f << 16), kCop1 | 33, "cvt.d", "fds" },
+ { kFpMask | (0x1f << 16), kCop1 | 36, "cvt.w", "fds" },
+ { kFpMask | (0x1f << 16), kCop1 | 37, "cvt.l", "fds" },
+ { kFpMask | (0x1f << 16), kCop1 | 38, "cvt.ps", "fds" },
+};
+
+static uint32_t ReadU32(const uint8_t* ptr) {
+ // We only support little-endian MIPS.
+ return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24);
+}
+
+static void DumpMips(std::ostream& os, const uint8_t* instr_ptr) {
+ uint32_t instruction = ReadU32(instr_ptr);
+
+ uint32_t rs = (instruction >> 21) & 0x1f; // I-type, R-type.
+ uint32_t rt = (instruction >> 16) & 0x1f; // I-type, R-type.
+ uint32_t rd = (instruction >> 11) & 0x1f; // R-type.
+ uint32_t sa = (instruction >> 6) & 0x1f; // R-type.
+
+ std::string opcode;
+ std::ostringstream args;
+
+ // TODO: remove this!
+ uint32_t op = (instruction >> 26) & 0x3f;
+ uint32_t function = (instruction & 0x3f); // R-type.
+ opcode = StringPrintf("op=%d fn=%d", op, function);
+
+ for (size_t i = 0; i < arraysize(gMipsInstructions); ++i) {
+ if (gMipsInstructions[i].Matches(instruction)) {
+ opcode = gMipsInstructions[i].name;
+ for (const char* args_fmt = gMipsInstructions[i].args_fmt; *args_fmt; ++args_fmt) {
+ switch (*args_fmt) {
+ case 'A': // sa (shift amount).
+ args << sa;
+ break;
+ case 'B': // Branch offset.
+ {
+ int32_t offset = static_cast<int16_t>(instruction & 0xffff);
+ offset <<= 2;
+ offset += 4; // Delay slot.
+ args << StringPrintf("%p ; %+d", instr_ptr + offset, offset);
+ }
+ break;
+ case 'D': args << 'r' << rd; break;
+ case 'd': args << 'f' << rd; break;
+ case 'f': // Floating point "fmt".
+ {
+ size_t fmt = (instruction >> 21) & 0x7; // TODO: other fmts?
+ switch (fmt) {
+ case 0: opcode += ".s"; break;
+ case 1: opcode += ".d"; break;
+ case 4: opcode += ".w"; break;
+ case 5: opcode += ".l"; break;
+ case 6: opcode += ".ps"; break;
+ default: opcode += ".?"; break;
+ }
+ continue; // No ", ".
+ }
+ break;
+ case 'I': // Upper 16-bit immediate.
+ args << reinterpret_cast<void*>((instruction & 0xffff) << 16);
+ break;
+ case 'i': // Sign-extended lower 16-bit immediate.
+ args << static_cast<int16_t>(instruction & 0xffff);
+ break;
+ case 'L': // Jump label.
+ {
+ // TODO: is this right?
+ uint32_t instr_index = (instruction & 0x1ffffff);
+ uint32_t target = (instr_index << 2);
+ target |= (reinterpret_cast<uintptr_t>(instr_ptr + 4) & 0xf0000000);
+ args << reinterpret_cast<void*>(target);
+ }
+ break;
+ case 'O': // +x(rs)
+ {
+ int32_t offset = static_cast<int16_t>(instruction & 0xffff);
+ args << StringPrintf("%+d(r%d)", offset, rs);
+ if (rs == 17) {
+ args << " ; ";
+ Thread::DumpThreadOffset(args, offset, 4);
+ }
+ }
+ break;
+ case 'S': args << 'r' << rs; break;
+ case 's': args << 'f' << rs; break;
+ case 'T': args << 'r' << rt; break;
+ case 't': args << 'f' << rt; break;
+ }
+ if (*(args_fmt + 1)) {
+ args << ", ";
+ }
+ }
+ break;
+ }
+ }
+
+ os << StringPrintf("%p: %08x\t%-7s ", instr_ptr, instruction, opcode.c_str()) << args.str() << '\n';
+}
+
+DisassemblerMips::DisassemblerMips() {
+}
+
+size_t DisassemblerMips::Dump(std::ostream& os, const uint8_t* begin) {
+ DumpMips(os, begin);
+ return 4;
+}
+
+void DisassemblerMips::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) {
+ for (const uint8_t* cur = begin; cur < end; cur += 4) {
+ DumpMips(os, cur);
+ }
+}
+
+} // namespace mips
+} // namespace art
diff --git a/disassembler/disassembler_mips.h b/disassembler/disassembler_mips.h
new file mode 100644
index 0000000..d386267
--- /dev/null
+++ b/disassembler/disassembler_mips.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ART_DISASSEMBLER_DISASSEMBLER_MIPS_H_
+#define ART_DISASSEMBLER_DISASSEMBLER_MIPS_H_
+
+#include <vector>
+
+#include "disassembler.h"
+
+namespace art {
+namespace mips {
+
+class DisassemblerMips : public Disassembler {
+ public:
+ DisassemblerMips();
+ virtual size_t Dump(std::ostream& os, const uint8_t* begin);
+ virtual void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end);
+
+ private:
+ DISALLOW_COPY_AND_ASSIGN(DisassemblerMips);
+};
+
+} // namespace mips
+} // namespace art
+
+#endif // ART_DISASSEMBLER_DISASSEMBLER_MIPS_H_
diff --git a/disassembler/disassembler_x86.cc b/disassembler/disassembler_x86.cc
new file mode 100644
index 0000000..e5cdb7b
--- /dev/null
+++ b/disassembler/disassembler_x86.cc
@@ -0,0 +1,750 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "disassembler_x86.h"
+
+#include <iostream>
+
+#include "base/logging.h"
+#include "base/stringprintf.h"
+#include "thread.h"
+
+namespace art {
+namespace x86 {
+
+DisassemblerX86::DisassemblerX86() {}
+
+size_t DisassemblerX86::Dump(std::ostream& os, const uint8_t* begin) {
+ return DumpInstruction(os, begin);
+}
+
+void DisassemblerX86::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) {
+ size_t length = 0;
+ for (const uint8_t* cur = begin; cur < end; cur += length) {
+ length = DumpInstruction(os, cur);
+ }
+}
+
+static const char* gReg8Names[] = { "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh" };
+static const char* gReg16Names[] = { "ax", "cx", "dx", "bx", "sp", "bp", "si", "di" };
+static const char* gReg32Names[] = { "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi" };
+
+static void DumpReg0(std::ostream& os, uint8_t /*rex*/, size_t reg,
+ bool byte_operand, uint8_t size_override) {
+ DCHECK_LT(reg, 8u);
+ // TODO: combine rex into size
+ size_t size = byte_operand ? 1 : (size_override == 0x66 ? 2 : 4);
+ switch (size) {
+ case 1: os << gReg8Names[reg]; break;
+ case 2: os << gReg16Names[reg]; break;
+ case 4: os << gReg32Names[reg]; break;
+ default: LOG(FATAL) << "unexpected size " << size;
+ }
+}
+
+enum RegFile { GPR, MMX, SSE };
+
+static void DumpReg(std::ostream& os, uint8_t rex, uint8_t reg,
+ bool byte_operand, uint8_t size_override, RegFile reg_file) {
+ size_t reg_num = reg; // TODO: combine with REX.R on 64bit
+ if (reg_file == GPR) {
+ DumpReg0(os, rex, reg_num, byte_operand, size_override);
+ } else if (reg_file == SSE) {
+ os << "xmm" << reg_num;
+ } else {
+ os << "mm" << reg_num;
+ }
+}
+
+static void DumpBaseReg(std::ostream& os, uint8_t rex, uint8_t reg) {
+ size_t reg_num = reg; // TODO: combine with REX.B on 64bit
+ DumpReg0(os, rex, reg_num, false, 0);
+}
+
+static void DumpIndexReg(std::ostream& os, uint8_t rex, uint8_t reg) {
+ int reg_num = reg; // TODO: combine with REX.X on 64bit
+ DumpReg0(os, rex, reg_num, false, 0);
+}
+
+enum SegmentPrefix {
+ kCs = 0x2e,
+ kSs = 0x36,
+ kDs = 0x3e,
+ kEs = 0x26,
+ kFs = 0x64,
+ kGs = 0x65,
+};
+
+static void DumpSegmentOverride(std::ostream& os, uint8_t segment_prefix) {
+ switch (segment_prefix) {
+ case kCs: os << "cs:"; break;
+ case kSs: os << "ss:"; break;
+ case kDs: os << "ds:"; break;
+ case kEs: os << "es:"; break;
+ case kFs: os << "fs:"; break;
+ case kGs: os << "gs:"; break;
+ default: break;
+ }
+}
+
+size_t DisassemblerX86::DumpInstruction(std::ostream& os, const uint8_t* instr) {
+ const uint8_t* begin_instr = instr;
+ bool have_prefixes = true;
+ uint8_t prefix[4] = {0, 0, 0, 0};
+ const char** modrm_opcodes = NULL;
+ do {
+ switch (*instr) {
+ // Group 1 - lock and repeat prefixes:
+ case 0xF0:
+ case 0xF2:
+ case 0xF3:
+ prefix[0] = *instr;
+ break;
+ // Group 2 - segment override prefixes:
+ case kCs:
+ case kSs:
+ case kDs:
+ case kEs:
+ case kFs:
+ case kGs:
+ prefix[1] = *instr;
+ break;
+ // Group 3 - operand size override:
+ case 0x66:
+ prefix[2] = *instr;
+ break;
+ // Group 4 - address size override:
+ case 0x67:
+ prefix[3] = *instr;
+ break;
+ default:
+ have_prefixes = false;
+ break;
+ }
+ if (have_prefixes) {
+ instr++;
+ }
+ } while (have_prefixes);
+ uint8_t rex = (*instr >= 0x40 && *instr <= 0x4F) ? *instr : 0;
+ bool has_modrm = false;
+ bool reg_is_opcode = false;
+ size_t immediate_bytes = 0;
+ size_t branch_bytes = 0;
+ std::ostringstream opcode;
+ bool store = false; // stores to memory (ie rm is on the left)
+ bool load = false; // loads from memory (ie rm is on the right)
+ bool byte_operand = false;
+ bool ax = false; // implicit use of ax
+ bool cx = false; // implicit use of cx
+ bool reg_in_opcode = false; // low 3-bits of opcode encode register parameter
+ bool no_ops = false;
+ RegFile src_reg_file = GPR;
+ RegFile dst_reg_file = GPR;
+ switch (*instr) {
+#define DISASSEMBLER_ENTRY(opname, \
+ rm8_r8, rm32_r32, \
+ r8_rm8, r32_rm32, \
+ ax8_i8, ax32_i32) \
+ case rm8_r8: opcode << #opname; store = true; has_modrm = true; byte_operand = true; break; \
+ case rm32_r32: opcode << #opname; store = true; has_modrm = true; break; \
+ case r8_rm8: opcode << #opname; load = true; has_modrm = true; byte_operand = true; break; \
+ case r32_rm32: opcode << #opname; load = true; has_modrm = true; break; \
+ case ax8_i8: opcode << #opname; ax = true; immediate_bytes = 1; byte_operand = true; break; \
+ case ax32_i32: opcode << #opname; ax = true; immediate_bytes = 4; break;
+
+DISASSEMBLER_ENTRY(add,
+ 0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */,
+ 0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */,
+ 0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */)
+DISASSEMBLER_ENTRY(or,
+ 0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */,
+ 0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */,
+ 0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */)
+DISASSEMBLER_ENTRY(adc,
+ 0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */,
+ 0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */,
+ 0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */)
+DISASSEMBLER_ENTRY(sbb,
+ 0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */,
+ 0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */,
+ 0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */)
+DISASSEMBLER_ENTRY(and,
+ 0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */,
+ 0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */,
+ 0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */)
+DISASSEMBLER_ENTRY(sub,
+ 0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */,
+ 0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */,
+ 0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */)
+DISASSEMBLER_ENTRY(xor,
+ 0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */,
+ 0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */,
+ 0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */)
+DISASSEMBLER_ENTRY(cmp,
+ 0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */,
+ 0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */,
+ 0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */)
+
+#undef DISASSEMBLER_ENTRY
+ case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
+ opcode << "push";
+ reg_in_opcode = true;
+ break;
+ case 0x58: case 0x59: case 0x5A: case 0x5B: case 0x5C: case 0x5D: case 0x5E: case 0x5F:
+ opcode << "pop";
+ reg_in_opcode = true;
+ break;
+ case 0x68: opcode << "push"; immediate_bytes = 4; break;
+ case 0x6A: opcode << "push"; immediate_bytes = 1; break;
+ case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
+ case 0x78: case 0x79: case 0x7A: case 0x7B: case 0x7C: case 0x7D: case 0x7E: case 0x7F:
+ static const char* condition_codes[] =
+ {"o", "no", "b/nae/c", "nb/ae/nc", "z/eq", "nz/ne", "be/na", "nbe/a",
+ "s", "ns", "p/pe", "np/po", "l/nge", "nl/ge", "le/ng", "nle/g"
+ };
+ opcode << "j" << condition_codes[*instr & 0xF];
+ branch_bytes = 1;
+ break;
+ case 0x88: opcode << "mov"; store = true; has_modrm = true; byte_operand = true; break;
+ case 0x89: opcode << "mov"; store = true; has_modrm = true; break;
+ case 0x8A: opcode << "mov"; load = true; has_modrm = true; byte_operand = true; break;
+ case 0x8B: opcode << "mov"; load = true; has_modrm = true; break;
+
+ case 0x0F: // 2 byte extended opcode
+ instr++;
+ switch (*instr) {
+ case 0x10: case 0x11:
+ if (prefix[0] == 0xF2) {
+ opcode << "movsd";
+ prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else if (prefix[0] == 0xF3) {
+ opcode << "movss";
+ prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else if (prefix[2] == 0x66) {
+ opcode << "movupd";
+ prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else {
+ opcode << "movups";
+ }
+ has_modrm = true;
+ src_reg_file = dst_reg_file = SSE;
+ load = *instr == 0x10;
+ store = !load;
+ break;
+ case 0x2A:
+ if (prefix[2] == 0x66) {
+ opcode << "cvtpi2pd";
+ prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else if (prefix[0] == 0xF2) {
+ opcode << "cvtsi2sd";
+ prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else if (prefix[0] == 0xF3) {
+ opcode << "cvtsi2ss";
+ prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else {
+ opcode << "cvtpi2ps";
+ }
+ load = true;
+ has_modrm = true;
+ dst_reg_file = SSE;
+ break;
+ case 0x2C:
+ if (prefix[2] == 0x66) {
+ opcode << "cvttpd2pi";
+ prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else if (prefix[0] == 0xF2) {
+ opcode << "cvttsd2si";
+ prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else if (prefix[0] == 0xF3) {
+ opcode << "cvttss2si";
+ prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else {
+ opcode << "cvttps2pi";
+ }
+ load = true;
+ has_modrm = true;
+ src_reg_file = SSE;
+ break;
+ case 0x2D:
+ if (prefix[2] == 0x66) {
+ opcode << "cvtpd2pi";
+ prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else if (prefix[0] == 0xF2) {
+ opcode << "cvtsd2si";
+ prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else if (prefix[0] == 0xF3) {
+ opcode << "cvtss2si";
+ prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else {
+ opcode << "cvtps2pi";
+ }
+ load = true;
+ has_modrm = true;
+ src_reg_file = SSE;
+ break;
+ case 0x2E:
+ opcode << "u";
+ // FALLTHROUGH
+ case 0x2F:
+ if (prefix[2] == 0x66) {
+ opcode << "comisd";
+ prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else {
+ opcode << "comiss";
+ }
+ has_modrm = true;
+ load = true;
+ src_reg_file = dst_reg_file = SSE;
+ break;
+ case 0x38: // 3 byte extended opcode
+ opcode << StringPrintf("unknown opcode '0F 38 %02X'", *instr);
+ break;
+ case 0x3A: // 3 byte extended opcode
+ opcode << StringPrintf("unknown opcode '0F 3A %02X'", *instr);
+ break;
+ case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
+ case 0x58: case 0x59: case 0x5C: case 0x5D: case 0x5E: case 0x5F: {
+ switch (*instr) {
+ case 0x50: opcode << "movmsk"; break;
+ case 0x51: opcode << "sqrt"; break;
+ case 0x52: opcode << "rsqrt"; break;
+ case 0x53: opcode << "rcp"; break;
+ case 0x54: opcode << "and"; break;
+ case 0x55: opcode << "andn"; break;
+ case 0x56: opcode << "or"; break;
+ case 0x57: opcode << "xor"; break;
+ case 0x58: opcode << "add"; break;
+ case 0x59: opcode << "mul"; break;
+ case 0x5C: opcode << "sub"; break;
+ case 0x5D: opcode << "min"; break;
+ case 0x5E: opcode << "div"; break;
+ case 0x5F: opcode << "max"; break;
+ default: LOG(FATAL) << "Unreachable";
+ }
+ if (prefix[2] == 0x66) {
+ opcode << "pd";
+ prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else if (prefix[0] == 0xF2) {
+ opcode << "sd";
+ prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else if (prefix[0] == 0xF3) {
+ opcode << "ss";
+ prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else {
+ opcode << "ps";
+ }
+ load = true;
+ has_modrm = true;
+ src_reg_file = dst_reg_file = SSE;
+ break;
+ }
+ case 0x5A:
+ if (prefix[2] == 0x66) {
+ opcode << "cvtpd2ps";
+ prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else if (prefix[0] == 0xF2) {
+ opcode << "cvtsd2ss";
+ prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else if (prefix[0] == 0xF3) {
+ opcode << "cvtss2sd";
+ prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else {
+ opcode << "cvtps2pd";
+ }
+ load = true;
+ has_modrm = true;
+ src_reg_file = dst_reg_file = SSE;
+ break;
+ case 0x5B:
+ if (prefix[2] == 0x66) {
+ opcode << "cvtps2dq";
+ prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else if (prefix[0] == 0xF2) {
+ opcode << "bad opcode F2 0F 5B";
+ } else if (prefix[0] == 0xF3) {
+ opcode << "cvttps2dq";
+ prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else {
+ opcode << "cvtdq2ps";
+ }
+ load = true;
+ has_modrm = true;
+ src_reg_file = dst_reg_file = SSE;
+ break;
+ case 0x6E:
+ if (prefix[2] == 0x66) {
+ dst_reg_file = SSE;
+ prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else {
+ dst_reg_file = MMX;
+ }
+ opcode << "movd";
+ load = true;
+ has_modrm = true;
+ break;
+ case 0x6F:
+ if (prefix[2] == 0x66) {
+ dst_reg_file = SSE;
+ opcode << "movdqa";
+ prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else if (prefix[0] == 0xF3) {
+ dst_reg_file = SSE;
+ opcode << "movdqu";
+ prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else {
+ dst_reg_file = MMX;
+ opcode << "movq";
+ }
+ load = true;
+ has_modrm = true;
+ break;
+ case 0x71:
+ if (prefix[2] == 0x66) {
+ dst_reg_file = SSE;
+ prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else {
+ dst_reg_file = MMX;
+ }
+ static const char* x71_opcodes[] = {"unknown-71", "unknown-71", "psrlw", "unknown-71", "psraw", "unknown-71", "psllw", "unknown-71"};
+ modrm_opcodes = x71_opcodes;
+ reg_is_opcode = true;
+ has_modrm = true;
+ store = true;
+ immediate_bytes = 1;
+ break;
+ case 0x72:
+ if (prefix[2] == 0x66) {
+ dst_reg_file = SSE;
+ prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else {
+ dst_reg_file = MMX;
+ }
+ static const char* x72_opcodes[] = {"unknown-72", "unknown-72", "psrld", "unknown-72", "psrad", "unknown-72", "pslld", "unknown-72"};
+ modrm_opcodes = x72_opcodes;
+ reg_is_opcode = true;
+ has_modrm = true;
+ store = true;
+ immediate_bytes = 1;
+ break;
+ case 0x73:
+ if (prefix[2] == 0x66) {
+ dst_reg_file = SSE;
+ prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else {
+ dst_reg_file = MMX;
+ }
+ static const char* x73_opcodes[] = {"unknown-73", "unknown-73", "psrlq", "unknown-73", "unknown-73", "unknown-73", "psllq", "unknown-73"};
+ modrm_opcodes = x73_opcodes;
+ reg_is_opcode = true;
+ has_modrm = true;
+ store = true;
+ immediate_bytes = 1;
+ break;
+ case 0x7E:
+ if (prefix[2] == 0x66) {
+ src_reg_file = SSE;
+ prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
+ } else {
+ src_reg_file = MMX;
+ }
+ opcode << "movd";
+ has_modrm = true;
+ store = true;
+ break;
+ case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
+ case 0x88: case 0x89: case 0x8A: case 0x8B: case 0x8C: case 0x8D: case 0x8E: case 0x8F:
+ opcode << "j" << condition_codes[*instr & 0xF];
+ branch_bytes = 4;
+ break;
+ case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
+ case 0x98: case 0x99: case 0x9A: case 0x9B: case 0x9C: case 0x9D: case 0x9E: case 0x9F:
+ opcode << "set" << condition_codes[*instr & 0xF];
+ modrm_opcodes = NULL;
+ reg_is_opcode = true;
+ has_modrm = true;
+ store = true;
+ break;
+ case 0xAE:
+ if (prefix[0] == 0xF3) {
+ prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
+ static const char* xAE_opcodes[] = {"rdfsbase", "rdgsbase", "wrfsbase", "wrgsbase", "unknown-AE", "unknown-AE", "unknown-AE", "unknown-AE"};
+ modrm_opcodes = xAE_opcodes;
+ reg_is_opcode = true;
+ has_modrm = true;
+ uint8_t reg_or_opcode = (instr[1] >> 3) & 7;
+ switch (reg_or_opcode) {
+ case 0:
+ prefix[1] = kFs;
+ load = true;
+ break;
+ case 1:
+ prefix[1] = kGs;
+ load = true;
+ break;
+ case 2:
+ prefix[1] = kFs;
+ store = true;
+ break;
+ case 3:
+ prefix[1] = kGs;
+ store = true;
+ break;
+ default:
+ load = true;
+ break;
+ }
+ } else {
+ static const char* xAE_opcodes[] = {"unknown-AE", "unknown-AE", "unknown-AE", "unknown-AE", "unknown-AE", "lfence", "mfence", "sfence"};
+ modrm_opcodes = xAE_opcodes;
+ reg_is_opcode = true;
+ has_modrm = true;
+ load = true;
+ no_ops = true;
+ }
+ break;
+ case 0xB1: opcode << "cmpxchg"; has_modrm = true; store = true; break;
+ case 0xB6: opcode << "movzxb"; has_modrm = true; load = true; break;
+ case 0xB7: opcode << "movzxw"; has_modrm = true; load = true; break;
+ case 0xBE: opcode << "movsxb"; has_modrm = true; load = true; break;
+ case 0xBF: opcode << "movsxw"; has_modrm = true; load = true; break;
+ default:
+ opcode << StringPrintf("unknown opcode '0F %02X'", *instr);
+ break;
+ }
+ break;
+ case 0x80: case 0x81: case 0x82: case 0x83:
+ static const char* x80_opcodes[] = {"add", "or", "adc", "sbb", "and", "sub", "xor", "cmp"};
+ modrm_opcodes = x80_opcodes;
+ has_modrm = true;
+ reg_is_opcode = true;
+ store = true;
+ byte_operand = (*instr & 1) == 0;
+ immediate_bytes = *instr == 0x81 ? 4 : 1;
+ break;
+ case 0x84: case 0x85:
+ opcode << "test";
+ has_modrm = true;
+ load = true;
+ byte_operand = (*instr & 1) == 0;
+ break;
+ case 0x8D:
+ opcode << "lea";
+ has_modrm = true;
+ load = true;
+ break;
+ case 0x8F:
+ opcode << "pop";
+ has_modrm = true;
+ reg_is_opcode = true;
+ store = true;
+ break;
+ case 0xB0: case 0xB1: case 0xB2: case 0xB3: case 0xB4: case 0xB5: case 0xB6: case 0xB7:
+ opcode << "mov";
+ immediate_bytes = 1;
+ reg_in_opcode = true;
+ break;
+ case 0xB8: case 0xB9: case 0xBA: case 0xBB: case 0xBC: case 0xBD: case 0xBE: case 0xBF:
+ opcode << "mov";
+ immediate_bytes = 4;
+ reg_in_opcode = true;
+ break;
+ case 0xC0: case 0xC1:
+ case 0xD0: case 0xD1: case 0xD2: case 0xD3:
+ static const char* shift_opcodes[] =
+ {"rol", "ror", "rcl", "rcr", "shl", "shr", "unknown-shift", "sar"};
+ modrm_opcodes = shift_opcodes;
+ has_modrm = true;
+ reg_is_opcode = true;
+ store = true;
+ immediate_bytes = ((*instr & 0xf0) == 0xc0) ? 1 : 0;
+ cx = (*instr == 0xD2) || (*instr == 0xD3);
+ byte_operand = (*instr == 0xC0);
+ break;
+ case 0xC3: opcode << "ret"; break;
+ case 0xC7:
+ static const char* c7_opcodes[] = {"mov", "unknown-c7", "unknown-c7", "unknown-c7", "unknown-c7", "unknown-c7", "unknown-c7", "unknown-c7"};
+ modrm_opcodes = c7_opcodes;
+ store = true;
+ immediate_bytes = 4;
+ has_modrm = true;
+ reg_is_opcode = true;
+ break;
+ case 0xCC: opcode << "int 3"; break;
+ case 0xE8: opcode << "call"; branch_bytes = 4; break;
+ case 0xE9: opcode << "jmp"; branch_bytes = 4; break;
+ case 0xEB: opcode << "jmp"; branch_bytes = 1; break;
+ case 0xF5: opcode << "cmc"; break;
+ case 0xF6: case 0xF7:
+ static const char* f7_opcodes[] = {"test", "unknown-f7", "not", "neg", "mul edx:eax, eax *", "imul edx:eax, eax *", "div edx:eax, edx:eax /", "idiv edx:eax, edx:eax /"};
+ modrm_opcodes = f7_opcodes;
+ has_modrm = true;
+ reg_is_opcode = true;
+ store = true;
+ immediate_bytes = ((instr[1] & 0x38) == 0) ? 1 : 0;
+ break;
+ case 0xFF:
+ static const char* ff_opcodes[] = {"inc", "dec", "call", "call", "jmp", "jmp", "push", "unknown-ff"};
+ modrm_opcodes = ff_opcodes;
+ has_modrm = true;
+ reg_is_opcode = true;
+ load = true;
+ break;
+ default:
+ opcode << StringPrintf("unknown opcode '%02X'", *instr);
+ break;
+ }
+ std::ostringstream args;
+ if (reg_in_opcode) {
+ DCHECK(!has_modrm);
+ DumpReg(args, rex, *instr & 0x7, false, prefix[2], GPR);
+ }
+ instr++;
+ uint32_t address_bits = 0;
+ if (has_modrm) {
+ uint8_t modrm = *instr;
+ instr++;
+ uint8_t mod = modrm >> 6;
+ uint8_t reg_or_opcode = (modrm >> 3) & 7;
+ uint8_t rm = modrm & 7;
+ std::ostringstream address;
+ if (mod == 0 && rm == 5) { // fixed address
+ address_bits = *reinterpret_cast<const uint32_t*>(instr);
+ address << StringPrintf("[0x%x]", address_bits);
+ instr += 4;
+ } else if (rm == 4 && mod != 3) { // SIB
+ uint8_t sib = *instr;
+ instr++;
+ uint8_t ss = (sib >> 6) & 3;
+ uint8_t index = (sib >> 3) & 7;
+ uint8_t base = sib & 7;
+ address << "[";
+ if (base != 5 || mod != 0) {
+ DumpBaseReg(address, rex, base);
+ if (index != 4) {
+ address << " + ";
+ }
+ }
+ if (index != 4) {
+ DumpIndexReg(address, rex, index);
+ if (ss != 0) {
+ address << StringPrintf(" * %d", 1 << ss);
+ }
+ }
+ if (mod == 1) {
+ address << StringPrintf(" + %d", *reinterpret_cast<const int8_t*>(instr));
+ instr++;
+ } else if (mod == 2) {
+ address << StringPrintf(" + %d", *reinterpret_cast<const int32_t*>(instr));
+ instr += 4;
+ }
+ address << "]";
+ } else {
+ if (mod == 3) {
+ if (!no_ops) {
+ DumpReg(address, rex, rm, byte_operand, prefix[2], load ? src_reg_file : dst_reg_file);
+ }
+ } else {
+ address << "[";
+ DumpBaseReg(address, rex, rm);
+ if (mod == 1) {
+ address << StringPrintf(" + %d", *reinterpret_cast<const int8_t*>(instr));
+ instr++;
+ } else if (mod == 2) {
+ address << StringPrintf(" + %d", *reinterpret_cast<const int32_t*>(instr));
+ instr += 4;
+ }
+ address << "]";
+ }
+ }
+
+ if (reg_is_opcode && modrm_opcodes != NULL) {
+ opcode << modrm_opcodes[reg_or_opcode];
+ }
+ if (load) {
+ if (!reg_is_opcode) {
+ DumpReg(args, rex, reg_or_opcode, byte_operand, prefix[2], dst_reg_file);
+ args << ", ";
+ }
+ DumpSegmentOverride(args, prefix[1]);
+ args << address.str();
+ } else {
+ DCHECK(store);
+ DumpSegmentOverride(args, prefix[1]);
+ args << address.str();
+ if (!reg_is_opcode) {
+ args << ", ";
+ DumpReg(args, rex, reg_or_opcode, byte_operand, prefix[2], src_reg_file);
+ }
+ }
+ }
+ if (ax) {
+ // If this opcode implicitly uses ax, ax is always the first arg.
+ DumpReg(args, rex, 0 /* EAX */, byte_operand, prefix[2], GPR);
+ }
+ if (cx) {
+ args << ", ";
+ DumpReg(args, rex, 1 /* ECX */, true, prefix[2], GPR);
+ }
+ if (immediate_bytes > 0) {
+ if (has_modrm || reg_in_opcode || ax || cx) {
+ args << ", ";
+ }
+ if (immediate_bytes == 1) {
+ args << StringPrintf("%d", *reinterpret_cast<const int8_t*>(instr));
+ instr++;
+ } else {
+ CHECK_EQ(immediate_bytes, 4u);
+ args << StringPrintf("%d", *reinterpret_cast<const int32_t*>(instr));
+ instr += 4;
+ }
+ } else if (branch_bytes > 0) {
+ DCHECK(!has_modrm);
+ int32_t displacement;
+ if (branch_bytes == 1) {
+ displacement = *reinterpret_cast<const int8_t*>(instr);
+ instr++;
+ } else {
+ CHECK_EQ(branch_bytes, 4u);
+ displacement = *reinterpret_cast<const int32_t*>(instr);
+ instr += 4;
+ }
+ args << StringPrintf("%+d (%p)", displacement, instr + displacement);
+ }
+ if (prefix[1] == kFs) {
+ args << " ; ";
+ Thread::DumpThreadOffset(args, address_bits, 4);
+ }
+ std::stringstream hex;
+ for (size_t i = 0; begin_instr + i < instr; ++i) {
+ hex << StringPrintf("%02X", begin_instr[i]);
+ }
+ std::stringstream prefixed_opcode;
+ switch (prefix[0]) {
+ case 0xF0: prefixed_opcode << "lock "; break;
+ case 0xF2: prefixed_opcode << "repne "; break;
+ case 0xF3: prefixed_opcode << "repe "; break;
+ case 0: break;
+ default: LOG(FATAL) << "Unreachable";
+ }
+ prefixed_opcode << opcode.str();
+ os << StringPrintf("%p: %22s \t%-7s ", begin_instr, hex.str().c_str(),
+ prefixed_opcode.str().c_str())
+ << args.str() << '\n';
+ return instr - begin_instr;
+} // NOLINT(readability/fn_size)
+
+} // namespace x86
+} // namespace art
diff --git a/disassembler/disassembler_x86.h b/disassembler/disassembler_x86.h
new file mode 100644
index 0000000..9adaff7
--- /dev/null
+++ b/disassembler/disassembler_x86.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ART_DISASSEMBLER_DISASSEMBLER_X86_H_
+#define ART_DISASSEMBLER_DISASSEMBLER_X86_H_
+
+#include "disassembler.h"
+
+namespace art {
+namespace x86 {
+
+class DisassemblerX86 : public Disassembler {
+ public:
+ DisassemblerX86();
+
+ virtual size_t Dump(std::ostream& os, const uint8_t* begin);
+ virtual void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end);
+ private:
+ size_t DumpInstruction(std::ostream& os, const uint8_t* instr);
+};
+
+} // namespace x86
+} // namespace art
+
+#endif // ART_DISASSEMBLER_DISASSEMBLER_X86_H_