/*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 * Authors: Thomas Abraham <thomas.ab@samsung.com>
 *         Chander Kashyap <k.chander@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Common Clock Framework support for Exynos7872 SoC.
 */

#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <soc/samsung/cal-if.h>
#include <dt-bindings/clock/exynos7872.h>

#include "../../soc/samsung/cal-if/exynos7872/cmucal-vclk.h"
#include "../../soc/samsung/cal-if/exynos7872/cmucal-node.h"
#include "../../soc/samsung/cal-if/exynos7872/cmucal-qch.h"
#include "../../soc/samsung/cal-if/exynos7872/clkout_exynos7872.h"
#include "composite.h"

static struct samsung_clk_provider *exynos7872_clk_provider;
/*
 * list of controller registers to be saved and restored during a
 * suspend/resume cycle.
 */
/* fixed rate clocks generated outside the soc */
struct samsung_fixed_rate exynos7872_fixed_rate_ext_clks[] __initdata = {
	FRATE(OSCCLK, "fin_pll", NULL, CLK_IS_ROOT, 26000000),
};

struct init_vclk exynos7872_apm_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_APM_BUS, MUX_CLKCMU_APM_BUS_USER, "UMUX_CLKCMU_APM_BUS", NULL, 0, VCLK_GATE, NULL),

	HWACG_VCLK(GATE_APM_SYS, APM_QCH_SYS, "GATE_APM_SYS", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_APM_CPU, APM_QCH_CPU, "GATE_APM_CPU", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MAILBOX_APM2AP, MAILBOX_APM2AP_QCH, "GATE_MAILBOX_APM2AP", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MAILBOX_APM2CP, MAILBOX_APM2CP_QCH, "GATE_MAILBOX_APM2CP", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MAILBOX_APM2GNSS, MAILBOX_APM2GNSS_QCH, "GATE_MAILBOX_APM2GNSS", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MAILBOX_APM2WLBT, MAILBOX_APM2WLBT_QCH, "GATE_MAILBOX_APM2WLBT", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I2C_APM, I2C_APM_QCH, "GATE_I2C_APM", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPEEDY_APM, SPEEDY_QCH, "GATE_SPEEDY_APM", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_WDT_APM, WDT_APM_QCH, "GATE_WDT_APM", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos7872_cmu_hwacg_vclks[] __initdata = {
	HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK0, DFTMUX_TOP_QCH_CLK_CSIS0, "GATE_DFTMUX_TOP_CIS_CLK0", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK1, DFTMUX_TOP_QCH_CLK_CSIS1, "GATE_DFTMUX_TOP_CIS_CLK1", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK2, DFTMUX_TOP_QCH_CLK_CSIS2, "GATE_DFTMUX_TOP_CIS_CLK2", NULL, 0, VCLK_GATE, NULL),
};

struct init_vclk exynos7872_dispaud_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_DISPAUD_BUS, MUX_CLKCMU_DISPAUD_BUS_USER, "UMUX_CLKCMU_DISPAUD_BUS", NULL, 0, VCLK_GATE, NULL),

	HWACG_VCLK(GATE_ABOX_ABOX, ABOX_QCH_ABOX, "GATE_ABOX_ABOX", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ABOX_CPU, ABOX_QCH_CPU, "GATE_ABOX_CPU", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ABOX_BUS, ABOX_QCH_BUS, "GATE_ABOX_BUS", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_UAIF0, ABOX_QCH_UAIF0, "GATE_UAIF0", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_UAIF2, ABOX_QCH_UAIF2, "GATE_UAIF2", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_UAIF3, ABOX_QCH_UAIF3, "GATE_UAIF3", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_FM, ABOX_QCH_FM, "GATE_FM", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_WDT_ABOXCPU, WDT_ABOXCPU_QCH, "GATE_WDT_ABOXCPU", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DPU_DPP, DPU_QCH_DPP, "GATE_DPU_DPP", "UMUX_CLKCMU_DISPAUD_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DPU_DMA, DPU_QCH_DMA, "GATE_DPU_DMA", "UMUX_CLKCMU_DISPAUD_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DPU_DECON0, DPU_QCH_DECON0, "GATE_DPU_QCH_DECON0", "UMUX_CLKCMU_DISPAUD_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SMMU_ABOX, SMMU_ABOX_QCH, "GATE_SMMU_ABOX", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SMMU_DPU, SMMU_DPU_QCH, "GATE_SMMU_DPU", "UMUX_CLKCMU_DISPAUD_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos7872_fsys_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_FSYS_BUS, MUX_CLKCMU_FSYS_BUS_USER, "UMUX_CLKCMU_FSYS_BUS", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS_MMC_CARD, MUX_CLKCMU_FSYS_MMC_CARD_USER, "UMUX_CLKCMU_FSYS_MMC_CARD", "UMUX_CLKCMU_FSYS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS_MMC_EMBD, MUX_CLKCMU_FSYS_MMC_EMBD_USER, "UMUX_CLKCMU_FSYS_MMC_EMBD", "UMUX_CLKCMU_FSYS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS_MMC_SDIO, MUX_CLKCMU_FSYS_MMC_SDIO_USER, "UMUX_CLKCMU_FSYS_MMC_SDIO", "UMUX_CLKCMU_FSYS_BUS", 0, VCLK_GATE, NULL),

	HWACG_VCLK(GATE_MMC_CARD, MMC_CARD_QCH, "GATE_MMC_CARD", "UMUX_CLKCMU_FSYS_MMC_CARD", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MMC_EMBD, MMC_EMBD_QCH, "GATE_MMC_EMBD", "UMUX_CLKCMU_FSYS_MMC_EMBD", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MMC_SDIO, MMC_SDIO_QCH, "GATE_MMC_SDIO", "UMUX_CLKCMU_FSYS_MMC_SDIO", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_RTIC, RTIC_QCH, "GATE_RTIC", "UMUX_CLKCMU_FSYS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SSS, SSS_QCH, "GATE_SSS", "UMUX_CLKCMU_FSYS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USB20DRD_HSDRD, USB20DRD_QCH_HSDRD, "GATE_USB20DRD_HSDRD", "UMUX_CLKCMU_FSYS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USB20DRD_USB, USB20DRD_QCH_USB, "GATE_USB20DRD_USB", "UMUX_CLKCMU_FSYS_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos7872_g3d_hwacg_vclks[] __initdata = {
	HWACG_VCLK(GATE_AGPU_G3D, AGPU_QCH, "GATE_AGPU_G3D", NULL, 0, VCLK_GATE, NULL),
};

struct init_vclk exynos7872_isp_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_IS_VRA, MUX_CLKCMU_IS_VRA_USER, "UMUX_CLKCMU_IS_VRA", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKCMU_IS_ISP, MUX_CLKCMU_IS_ISP_USER, "UMUX_CLKCMU_IS_ISP", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKCMU_IS_3AA, MUX_CLKCMU_IS_3AA_USER, "UMUX_CLKCMU_IS_3AA", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKCMU_IS_TPU, MUX_CLKCMU_IS_TPU_USER, "UMUX_CLKCMU_IS_TPU", NULL, 0, VCLK_GATE, NULL),

	HWACG_VCLK(GATE_IS5P15P0_IS_ISP, IS5P15P0_IS_QCH_ISP, "GATE_IS5P15P0_IS_ISP", "UMUX_CLKCMU_IS_ISP", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS5P15P0_IS_MCSC, IS5P15P0_IS_QCH_MCSC, "GATE_IS5P15P0_IS_MCSC", "UMUX_CLKCMU_IS_ISP", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS5P15P0_IS_VRA, IS5P15P0_IS_QCH_VRA, "GATE_IS5P15P0_IS_VRA", "UMUX_CLKCMU_IS_VRA", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS5P15P0_IS_CSIS_0, IS5P15P0_IS_QCH_CSIS_0, "GATE_IS5P15P0_IS_CSIS_0", "UMUX_CLKCMU_IS_3AA", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS5P15P0_IS_CSIS_1, IS5P15P0_IS_QCH_CSIS_1, "GATE_IS5P15P0_IS_CSIS_1", "UMUX_CLKCMU_IS_3AA", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS5P15P0_IS_IS_3AA, IS5P15P0_IS_QCH_IS_3AA, "GATE_IS5P15P0_IS_IS_3AA", "UMUX_CLKCMU_IS_3AA", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS5P15P0_IS_TPU, IS5P15P0_IS_QCH_TPU, "GATE_IS5P15P0_IS_TPU", "UMUX_CLKCMU_IS_TPU", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS5P15P0_IS_CSIS_DMA, IS5P15P0_IS_QCH_CSIS_DMA, "GATE_IS5P15P0_IS_CSIS_DMA", "UMUX_CLKCMU_IS_3AA", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SMMU_IS, SMMU_IS_QCH, "GATE_SMMU_IS", "UMUX_CLKCMU_IS_3AA", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos7872_mfcmscl_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_MFCMSCL_MSCL, MUX_CLKCMU_MFCMSCL_MSCL_USER, "UMUX_CLKCMU_MFCMSCL_MSCL", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKCMU_MFCMSCL_MFC, MUX_CLKCMU_MFCMSCL_MFC_USER, "UMUX_CLKCMU_MFCMSCL_MFC","UMUX_CLKCMU_MFCMSCL_MSCL", 0, VCLK_GATE, NULL),

	HWACG_VCLK(GATE_G2D, G2D_QCH, "GATE_G2D", "UMUX_CLKCMU_MFCMSCL_MSCL", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_JPEG, JPEG_QCH, "GATE_JPEG", "UMUX_CLKCMU_MFCMSCL_MSCL", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MFC, MFC_QCH, "GATE_MFC", "UMUX_CLKCMU_MFCMSCL_MFC", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MSCL, MSCL_QCH, "GATE_MSCL", "UMUX_CLKCMU_MFCMSCL_MSCL", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SMMU_MFCMSCL, SMMU_MFCMSCL_QCH, "GATE_SMMU_MFCMSCL", "UMUX_CLKCMU_MFCMSCL_MSCL", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos7872_mif_hwacg_vclks[] __initdata = {
	HWACG_VCLK(GATE_WRAP_ADC_IF_0, WRAP_ADC_IF_QCH_0, "GATE_WRAP_ADC_IF_0", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_WRAP_ADC_IF_1, WRAP_ADC_IF_QCH_1, "GATE_WRAP_ADC_IF_1", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PDMA, PDMA_CORE_QCH, "GATE_PDMA", NULL, 0, VCLK_GATE, NULL),
};

struct init_vclk exynos7872_peri_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_PERI_BUS, MUX_CLKCMU_PERI_BUS_USER, "UMUX_CLKCMU_PERI_BUS", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERI_UART_0, MUX_CLKCMU_PERI_UART_0_USER, "UMUX_CLKCMU_PERI_UART_0", "UMUX_CLKCMU_PERI_BUS_USER", 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERI_UART_1, MUX_CLKCMU_PERI_UART_1_USER, "UMUX_CLKCMU_PERI_UART_1", "UMUX_CLKCMU_PERI_BUS_USER", 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERI_UART_2, MUX_CLKCMU_PERI_UART_2_USER, "UMUX_CLKCMU_PERI_UART_2", "UMUX_CLKCMU_PERI_BUS_USER", 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERI_USI0, MUX_CLKCMU_PERI_USI0_USER, "UMUX_CLKCMU_PERI_USI0", "UMUX_CLKCMU_PERI_BUS_USER", 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERI_USI1, MUX_CLKCMU_PERI_USI1_USER, "UMUX_CLKCMU_PERI_USI1", "UMUX_CLKCMU_PERI_BUS_USER", 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERI_USI2, MUX_CLKCMU_PERI_USI2_USER, "UMUX_CLKCMU_PERI_USI2", "UMUX_CLKCMU_PERI_BUS_USER", 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERI_SPI0, MUX_CLKCMU_PERI_SPI0_USER, "UMUX_CLKCMU_PERI_SPI0", "UMUX_CLKCMU_PERI_BUS_USER", 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERI_SPI1, MUX_CLKCMU_PERI_SPI1_USER, "UMUX_CLKCMU_PERI_SPI1", "UMUX_CLKCMU_PERI_BUS_USER", 0, VCLK_GATE, NULL),

	HWACG_VCLK(GATE_BUSIF_TMU, BUSIF_TMU_QCH, "GATE_BUSIF_TMU", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PWM_MOTOR, LBLK_PERIC_QCH_PWM_MOTOR, "GATE_PWM_MOTOR", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I2C0, LBLK_PERIC_QCH_I2C0, "GATE_I2C0", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I2C1, LBLK_PERIC_QCH_I2C1, "GATE_I2C1", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I2C2, LBLK_PERIC_QCH_I2C2, "GATE_I2C2", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I2C3, LBLK_PERIC_QCH_I2C3, "GATE_I2C3", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I2C4, LBLK_PERIC_QCH_I2C4, "GATE_I2C4", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I2C5, LBLK_PERIC_QCH_I2C5, "GATE_I2C5", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I2C6, LBLK_PERIC_QCH_I2C6, "GATE_I2C6", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPI0, LBLK_PERIC_QCH_SPI0, "GATE_SPI0", "UMUX_CLKCMU_PERI_SPI0", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPI1, LBLK_PERIC_QCH_SPI1, "GATE_SPI1", "UMUX_CLKCMU_PERI_SPI1", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_HSI2C0, LBLK_PERIC_QCH_HSI2C0, "GATE_HSI2C0", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_HSI2C1, LBLK_PERIC_QCH_HSI2C1, "GATE_HSI2C1", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_HSI2C2, LBLK_PERIC_QCH_HSI2C2, "GATE_HSI2C2", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_HSI2C3, LBLK_PERIC_QCH_HSI2C3, "GATE_HSI2C3", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI0, LBLK_PERIC_QCH_USI0, "GATE_USI0", "UMUX_CLKCMU_PERI_USI0", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
	HWACG_VCLK(GATE_USI1, LBLK_PERIC_QCH_USI1, "GATE_USI1", "UMUX_CLKCMU_PERI_USI1", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
	HWACG_VCLK(GATE_USI2, LBLK_PERIC_QCH_USI2, "GATE_USI2", "UMUX_CLKCMU_PERI_USI2", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
	HWACG_VCLK(GATE_UART0, LBLK_PERIC_QCH_UART0, "GATE_UART0", "UMUX_CLKCMU_PERI_UART_0", 0, VCLK_GATE, "console-pclk0"),
	HWACG_VCLK(GATE_UART1, LBLK_PERIC_QCH_UART1, "GATE_UART1", "UMUX_CLKCMU_PERI_UART_1", 0, VCLK_GATE, "console-pclk1"),
	HWACG_VCLK(GATE_UART2, LBLK_PERIC_QCH_UART2, "GATE_UART2", "UMUX_CLKCMU_PERI_UART_2", 0, VCLK_GATE, "console-pclk2"),
	HWACG_VCLK(GATE_MCT, MCT_QCH, "GATE_MCT", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_OTP_CON_TOP, OTP_CON_TOP_QCH, "GATE_OTP_CON_TOP", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SECUCON, SECUCON_QCH, "GATE_SECUCON", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_WDT_CLUSTER0, WDT_CLUSTER0_QCH, "GATE_WDT_CLUSTER0", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_WDT_CLUSTER1, WDT_CLUSTER1_QCH, "GATE_WDT_CLUSTER1", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
};

static struct init_vclk exynos7872_clkout_vclks[] __initdata = {
	VCLK(OSCCLK_NFC, VCLK_CLKOUT1, "OSCCLK_NFC", 0, 0, NULL),
	VCLK(OSCCLK_AUD, VCLK_CLKOUT0, "OSCCLK_AUD", 0, 0, NULL),
};

/* Special VCLK */
struct init_vclk exynos7872_fsys_vclks[] __initdata = {
	VCLK(MMC_EMBD, VCLK_SPL_CLK_FSYS_MMC_EMBD_BLK_CMU, "MMC_EMBD", 0, 0, NULL),
	VCLK(MMC_CARD, VCLK_SPL_CLK_FSYS_MMC_CARD_BLK_CMU, "MMC_CARD", 0, 0, NULL),
	VCLK(MMC_SDIO, VCLK_SPL_CLK_FSYS_MMC_SDIO_BLK_CMU, "MMC_SDIO", 0, 0, NULL),
	VCLK(WIFI2AP_USBPLL, VCLK_WPLL_USBPLL, "WIFI2AP_USBPLL", 0, 0, NULL),
};

struct init_vclk exynos7872_cmu_vclks[] __initdata = {
	VCLK(CIS_CLK0, VCLK_CLKCMU_CIS_CLK0_BLK_CMU, "CIS_CLK0", 0, 0, NULL),
	VCLK(CIS_CLK1, VCLK_CLKCMU_CIS_CLK1_BLK_CMU, "CIS_CLK1", 0, 0, NULL),
	VCLK(CIS_CLK2, VCLK_CLKCMU_CIS_CLK2_BLK_CMU, "CIS_CLK2", 0, 0, NULL),
};

struct init_vclk exynos7872_peri_vclks[] __initdata = {
	VCLK(UART_0, VCLK_SPL_CLK_PERI_UART_0_BLK_CMU, "UART_0", 0, 0, "console-sclk0"),
	VCLK(UART_1, VCLK_SPL_CLK_PERI_UART_1_BLK_CMU, "UART_1", 0, 0, "console-sclk1"),
	VCLK(UART_2, VCLK_SPL_CLK_PERI_UART_2_BLK_CMU, "UART_2", 0, 0, "console-sclk2"),
	VCLK(SPI_0, VCLK_SPL_CLK_PERI_SPI_0_BLK_CMU, "SPI_0", 0, 0, NULL),
	VCLK(SPI_1, VCLK_SPL_CLK_PERI_SPI_1_BLK_CMU, "SPI_1", 0, 0, NULL),
	VCLK(USI0, VCLK_SPL_CLK_PERI_USI0_BLK_CMU, "USI0", 0, 0, NULL),
	VCLK(USI1, VCLK_SPL_CLK_PERI_USI1_BLK_CMU, "USI1", 0, 0, NULL),
	VCLK(USI2, VCLK_SPL_CLK_PERI_USI2_BLK_CMU, "USI2", 0, 0, NULL),
};

struct init_vclk exynos7872_dispaud_vclks[] __initdata = {
	VCLK(DOUT_CLK_ABOX_AUDIF, DIV_CLK_AUD_AUDIF, "DOUT_CLK_ABOX_AUDIF", 0, 0, NULL),
	VCLK(DOUT_CLK_ABOX_UAIF0, DIV_CLK_AUD_UAIF0, "DOUT_CLK_ABOX_UAIF0", 0, 0, NULL),
	VCLK(DOUT_CLK_ABOX_UAIF2, DIV_CLK_AUD_UAIF2, "DOUT_CLK_ABOX_UAIF2", 0, 0, NULL),
	VCLK(DOUT_CLK_ABOX_UAIF3, DIV_CLK_AUD_UAIF3, "DOUT_CLK_ABOX_UAIF3", 0, 0, NULL),
	VCLK(PLL_OUT_AUD, PLL_AUD, "PLL_OUT_AUD", 0, 0, NULL),
};

struct init_vclk exynos7872_dvfs_vclks[] __initdata = {
	VCLK(DFS_ABOX, VCLK_DFS_ABOX, "dfs_abox", 0, VCLK_DFS, NULL),
};

static __initdata struct of_device_id ext_clk_match[] = {
	{.compatible = "samsung,exynos7872-oscclk", .data = (void *)0},
	{},
};

void exynos7872_vclk_init(void)
{
}

/* register exynos7872 clocks */
void __init exynos7872_clk_init(struct device_node *np)
{
	void __iomem *reg_base;
	int ret;

	if (np) {
		reg_base = of_iomap(np, 0);
		if (!reg_base)
			panic("%s: failed to map registers\n", __func__);
	} else {
		panic("%s: unable to determine soc\n", __func__);
	}

	ret = cal_if_init(np);
	if (ret)
		panic("%s: unable to initialize cal-if\n", __func__);

	exynos7872_clk_provider = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
	if (!exynos7872_clk_provider)
		panic("%s: unable to allocate context.\n", __func__);

	samsung_register_of_fixed_ext(exynos7872_clk_provider, exynos7872_fixed_rate_ext_clks,
					  ARRAY_SIZE(exynos7872_fixed_rate_ext_clks),
					  ext_clk_match);
	/* register HWACG vclk */
	samsung_register_vclk(exynos7872_clk_provider, exynos7872_apm_hwacg_vclks, ARRAY_SIZE(exynos7872_apm_hwacg_vclks));
	samsung_register_vclk(exynos7872_clk_provider, exynos7872_cmu_hwacg_vclks, ARRAY_SIZE(exynos7872_cmu_hwacg_vclks));
	samsung_register_vclk(exynos7872_clk_provider, exynos7872_dispaud_hwacg_vclks, ARRAY_SIZE(exynos7872_dispaud_hwacg_vclks));
	samsung_register_vclk(exynos7872_clk_provider, exynos7872_fsys_hwacg_vclks, ARRAY_SIZE(exynos7872_fsys_hwacg_vclks));
	samsung_register_vclk(exynos7872_clk_provider, exynos7872_g3d_hwacg_vclks, ARRAY_SIZE(exynos7872_g3d_hwacg_vclks));
	samsung_register_vclk(exynos7872_clk_provider, exynos7872_isp_hwacg_vclks, ARRAY_SIZE(exynos7872_isp_hwacg_vclks));
	samsung_register_vclk(exynos7872_clk_provider, exynos7872_mfcmscl_hwacg_vclks, ARRAY_SIZE(exynos7872_mfcmscl_hwacg_vclks));
	samsung_register_vclk(exynos7872_clk_provider, exynos7872_mif_hwacg_vclks, ARRAY_SIZE(exynos7872_mif_hwacg_vclks));
	samsung_register_vclk(exynos7872_clk_provider, exynos7872_peri_hwacg_vclks, ARRAY_SIZE(exynos7872_peri_hwacg_vclks));

	/* register special vclk */
	samsung_register_vclk(exynos7872_clk_provider, exynos7872_fsys_vclks, ARRAY_SIZE(exynos7872_fsys_vclks));
	samsung_register_vclk(exynos7872_clk_provider, exynos7872_cmu_vclks, ARRAY_SIZE(exynos7872_cmu_vclks));
	samsung_register_vclk(exynos7872_clk_provider, exynos7872_peri_vclks, ARRAY_SIZE(exynos7872_peri_vclks));
	samsung_register_vclk(exynos7872_clk_provider, exynos7872_dispaud_vclks, ARRAY_SIZE(exynos7872_dispaud_vclks));
	samsung_register_vclk(exynos7872_clk_provider, exynos7872_clkout_vclks, ARRAY_SIZE(exynos7872_clkout_vclks));

	/* register DVFS vclk */
	samsung_register_vclk(exynos7872_clk_provider, exynos7872_dvfs_vclks, ARRAY_SIZE(exynos7872_dvfs_vclks));

	clk_register_fixed_factor(NULL, "pwm-clock", "fin_pll",CLK_SET_RATE_PARENT, 1, 1);

	samsung_clk_of_add_provider(np, exynos7872_clk_provider);

	late_time_init = exynos7872_vclk_init;

	pr_info("EXYNOS7872: Clock setup completed\n");
}

CLK_OF_DECLARE(exynos7872_clk, "samsung,exynos7872-clock", exynos7872_clk_init);